Philips TMS320C6713 manual Conclusion, McASP Error Handling and Management, McASP Summary

SPRA921

A typical usage for the frame sync pins is to carry the left-right clock (LRCLK) signal when transmitting and receiving stereo data. The frame sync signals are individually programmable for either internal or external generation, either bit or slot length, and either rising or falling edge polarity.

Some examples of the things that a system designer can use the McASP clocking flexibility for are:

•Input a high-frequency master clock (for example, 512fs of the receiver), receive with an internally generated bit clock ratio of /8, while transmitting with an internally generated bit clock ratio of /4 or /2. (An example application would be to receive data from a DVD at 48 kHz but output up-sampled or decoded audio at 96 kHz or 192 kHz.)

•Transmit/receive data based one sample rate (for example, 44.1 kHz) using McASP0 while transmitting and receiving at a different sample rate (for example, 48 kHz) on McASP1.

•Use the DSP’s on-board AUXCLK to supply the system clock when the input source is an A/D converter.

4.5McASP Error Handling and Management

To support the design of a robust audio system, the McASP module includes error-checking capability for the serial protocol, data underrun, and data overrun. In addition, each McASP includes a timer that continually measures the high-frequency master clock every 32-SYSCLK2 clock cycles. The timer value can be read to get a measurement of the high-frequency master clock frequency and has a min-max range setting that can raise an error flag if the high-frequency master clock goes out of a specified range.

Upon the detection of any one or more of the above errors (software selectable), or the assertion of the AMUTE_IN pin, the AMUTE output pin may be asserted to a high or low level (selectable) to immediately mute the audio output. In addition, an interrupt may be generated if enabled based on any one or more of the error sources.

4.6McASP Summary

The two McASPs on the TMS3206713 provide a total of 16 serial lines, independently programmable as transmit or receive. Each McASP has highly flexible independent clock and frame control for its receive and transmit group. Each serial line in turn supports multichannels of TDM data or alternatively direct interface to a variety of digital serial audio data transfer standards. The McASP enables a variety of serial audio interfaces needed in the breadth of high-performance multichannel audio applications.

5 Conclusion

The TMS320C6713 peripheral set enables the device to directly interface to a variety of components in these systems. The McASPs provide highly-flexible direct interconnect to the digital audio streams as well as high performance audio data converters. The two-level cache enables efficient data management and real time I/O while hiding performance issues associated with low cost external SDRAM. The TMS320C6713 DSP device architecture is ideally suited for multichannel, high-performance audio applications.

10TMS320C6713 Digital Signal Processor Optimized for High Performance Multichannel Audio Systems