SPRA921
•Glueless external memory interface (EMIF) capable of interfacing to SDRAM for bulk external storage of additional code or delay buffers. The EMIF also supports synchronous burst SRAM (SBSRAM), asynchronous memories, and peripherals with parallel interfaces.
•A
Figure 3 shows additional peripherals and the internal connection of the device. This includes:
•A highly efficient 16-channel enhanced direct memory access (EDMA) controller connects the peripherals to the internal and external memory. This controller can interleave transfers from different sources/destinations on a cycle-by-cycle basis, avoiding dead time of most DMAs when a higher priority transfer interrupts a lower priority one.
•Highly configurable PLL and clocking control logic to enable a variety of ratios of system and CPU clocks
•256K bytes of internal memory to provide a large internal program and data store
•Two multichannel buffered serial ports (McBSPs) provide general connection to multiple serial standards including SPI
•Two general-purpose timers to count system events or generate clock outputs
Optical |
| Optical |
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| RAM/ROM |
digital |
| digital |
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| |
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in |
| receiver |
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L
R Record out
Coaxial digital in
S/P DIF receiver
Multichannel
Multichannel analog
Multichannel analog in
L
R
L
R
Stereo L
analog R
in L
R
L
R
Tuner
Multiplexer
Multichannel
A to D
conversion
TMS320C6713 |
System |
controller |
D to A
conversion
out
Amp |
|
Amp |
|
Amp | Speaker |
| |
| level |
Amp | out |
| |
Amp |
|
| Subwoofer |
| out |
User displays | IR receiver |
and controls |
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Figure 1. Digital Surround Receiver Block Diagram
TMS320C6713 Digital Signal Processor Optimized for High Performance Multichannel Audio Systems | 3 |
