Philips UM10109 1.2 Pin configuration

© Koninklijke Philips Electronics N.V. 2005. All rights reserved.

User manual Rev. 02 — 23 May 2005 5 of 133

Philips Semiconductors UM10109

P89LPC932A1 User manual

1.1.4.8 Configuration byte protection

A separate write protection bit has been provided for the “configuration bytes”. These

bytes include UCFG1, BootStat, Boot Vector, and the sector security bytes. This write

protection applies for ISP and IAP modes. It does not apply to commercial programmer

modes. See Section 18.15 “Configuration byte protection” on page 119

1.1.5 Previous errata fix

Most known errata on the P89LPC932 devices has been fixed on the P89LPC932A1

device. For current errata information on the P89LPC932A1, if any, please see the

P89LPC932A1 errata sheet.

1.2 Pin configuration

Fig 1. P89LPC932A1 TSSOP28 pin configuration.

P89LPC932A1FDH

002aaa886

1

2

3

4

5

6

7

8

9

10

11

12

13

14

16

15

18

17

20

19

22

21

24

23

26

25

28

27

ICB/P2.0

OCD/P2.1

KBI0/CMP2/P0.0

OCC/P1.7

OCB/P1.6

RST/P1.5

VSS

XTAL1/P3.1

CLKOUT/XTAL2/P3.0

INT1/P1.4

SDA/INT0/P1.3

SCL/T0/P1.2

MOSI/P2.2

MISO/P2.3

P2.7/ICA

P2.6/OCA

P0.1/CIN2B/KBI1

P0.2/CIN2A/KBI2

P0.3/CIN1B/KBI3

P0.4/CIN1A/KBI4

P0.5/CMPREF/KBI5

VDD

P0.6/CMP1/KBI6

P0.7/T1/KBI7

P1.0/TXD

P1.1/RXD

P2.5/SPICLK

P2.4/SS

Contents

Main Contact information 1. Introduction 1.1 Comparison to the P89LPC932 device 1.1.1 Byte-erasability (IAP-Lite) 1.1.2 Serial in-circuit programming (ICP) 1.1.3 On-the-fly clock selection 1.1.4 Increased ISP/IAP functionality User manual Rev. 02 23 May 2005 5 of 133 1.1.5 Previous errata fix Fig 1. P89LPC932A1 TSSOP28 pin configuration. 1.2 Pin configuration P89LPC932A1FDH Fig 2. P89LPC932A1 PLCC28 pin configuration. Fig 3. P89LPC932A1 HVQFN28 pin configuration. P89LPC932A1FA P89LPC932A1FHN 1.3 Pin description P89LPC932A1 User manual Philips Semiconductors UM10109 P89LPC932A1 User manual Philips Semiconductors UM10109 Page Fig 4. P89LPC932A1 block diagram. P89LPC932A1 Page Page Page Page Page Page Page User manual Rev. 02 23 May 2005 20 of 133 1.5 Memory organization Fig 5. P89LPC932A1 memory map. 2. Clocks 2.1 Enhanced CPU 2.2 Clock definitions 2.2.1 Oscillator Clock (OSCCLK) 2.2.2 Low speed oscillator option 2.4 On-chip RC oscillator option 2.5 Watchdog oscillator option 2.6 External clock input option User manual Rev. 02 23 May 2005 23 of 133 2.7 Oscillator Clock (OSCCLK) wake-up delay Fig 7. Block diagram of oscillator control. Fig 6. Using the crystal oscillator. 2.8 CPU Clock (CCLK) modification: DIVM register 2.9 Low power select 3. Interrupts 3.1 Interrupt priority structure 3.2 External Interrupt pin glitch suppression Page 4. I/O ports 4.1 Port configurations 4.2 Quasi-bidirectional output configuration 4.3 Open drain output configuration 4.4 Input-only configuration 4.5 Push-pull output configuration 4.6 Port 0 and Analog Comparator functions 4.7 Additional port features 5. Power monitoring functions 5.1 Brownout detection 5.2 Power-on detection 5.3 Power reduction modes 6. Reset set. 6.1 Reset vector 7. Timers 0 and 1 7.1 Mode 0 Page Page 7.6 Timer overflow toggle output Fig 16. Timer/counter 0 or 1 in Mode 2 (8-bit auto-reload). Fig 18. Timer/counter 0 or 1 in mode 6 (PWM auto-reload). Fig 17. Timer/counter 0 Mode 3 (two 8-bit counters). 8. Real-time clock system timer 8.1 Real-time clock source 8.2 Changing RTCS1/RTCS0 8.3 Real-time clock interrupt/wake-up 8.4 Reset sources affecting the Real-time clock Page 9. Capture/Compare Unit (CCU) 9.1 CCU Clock (CCUCLK) 9.2 CCU Clock prescaling 9.3 Basic timer operation Page 9.4 Output compare Page 9.5 Input capture 9.6 PWM operation 9.7 Alternating output mode 9.8 Synchronized PWM register update 9.9 HALT 9.10 PLL operation Page Fig 24. Capture/compare unit interrupts. Page 10. UART 10.1 Mode 0 10.2 Mode 1 10.3 Mode 2 10.4 Mode 3 10.5 SFR space 10.6 Baud Rate generator and selection 10.7 Updating the BRGR1 and BRGR0 SFRs 10.8 Framing error 10.9 Break detect 10.10 More about UART Mode 0 10.11 More about UART Mode 1 10.12 More about UART Modes 2 and 3 Fig 27. Serial Port Mode 1 (only single transmit buffering case is shown). Fig 28. Serial Port Mode 2 or 3 (only single transmit buffering case is shown). If SM2 = 1 in modes 2 and 3, RI and FE behaves as in the following table. 10.13 Framing error and RI in Modes 2 and 3 with SM2 = 1 10.14 Break detect 10.15 Double buffering 10.16 Double buffering in different modes 10.17 Transmit interrupts with double buffering enabled (Modes 1, 2, and 3) 10.18 The 9th bit (bit 8) in double buffering (Modes 1, 2, and 3) 10.19 Multiprocessor communications 10.20 Automatic address recognition 11. I2C interface 11.1 I2C data register 11.2 I2C slave address register 11.3 I2C control register 11.4 I2C Status register 11.5 I2C SCL duty cycle registers I2SCLH and I2SCLL 11.6 I2C operation modes 11.6.1 Master Transmitter mode 11.6.2 Master Receiver mode 11.6.3 Slave Receiver mode 11.6.4 Slave Transmitter mode Fig 36. I2C serial interface block diagram. Page Page Page Page Page 12. Serial Peripheral Interface (SPI) Page Page Fig 39. SPI dual device configuration, where either can be a master or a slave. Fig 38. SPI single master single slave configuration. 12.1 Configuring the SPI 12.2 Additional considerations for a slave 12.3 Additional considerations for a master 12.4 Mode change on SS 12.5 Write collision 12.6 Data mode Fig 41. SPI slave transfer format with CPHA = 0. Fig 42. SPI slave transfer format with CPHA = 1. Fig 43. SPI master transfer format with CPHA = 0. 12.7 SPI clock prescaler select 13. Analog comparators 13.1 Comparator configuration Page 13.2 Internal reference voltage 13.3 Comparator input pins 13.4 Comparator interrupt 13.5 Comparators and power reduction modes 13.6 Comparators configuration example 14. Keypad interrupt (KBI) 15. Watchdog timer (WDT) 15.1 Watchdog function 15.2 Feed sequence Page Philips Semiconductors UM10109 The maximum number of tclks is: (3) Tabl e 89 shows sample P89LPC932A1 timeout values. tclks 2 ()255 1+()1 1048577=+= 15.3 Watchdog clock source 15.4 Watchdog Timer in Timer mode 15.5 Power-down operation 15.6 Periodic wake-up from power-down without an external oscillator 16. Additional features 16.1 Software reset 16.2 Dual Data Pointers 17. Data EEPROM 17.1 Data EEPROM read 17.2 Data EEPROM write 17.3 Hardware reset 17.4 Multiple writes to the DEEDAT register 17.5 Sequences of writes to DEECON and DEEDAT registers 17.6 Data EEPROM Row Fill 18. Flash memory 18.1 General description 18.2 Features Page Page Page 18.5 In-circuit programming (ICP) 18.6 ISP and IAP capabilities of the P89LPC932A1 18.7 Boot ROM 18.8 Power on reset code execution 18.9 Hardware activation of Boot Loader 18.10 In-system programming (ISP) 18.11 Using the In-system programming (ISP) Page Page 18.12 In-application programming (IAP) (This feature was not present in the original P89LPC932). 18.13 IAP authorization key 18.14 Flash write enable 18.15 Configuration byte protection 18.16 IAP error status Page Page 18.17 User configuration bytes 18.18 User security bytes This device has three security bits associated with each of its eight sectors, as shown in Table103 18.19 Boot Vector register 18.20 Boot status register Page 19. Instruction set Page Page Page 20. Disclaimers 21. Trademarks continued >> 22. Contents