Pioneer SX-3800 manual t t t, H H H

on the other hand, the broadcasting frequency is approachedfrom the iow frequency side (or when tuning away to a lower frequency) the pin no.4 voltage will be lower, resulting in Q22 being tumed on to light up the lower frequency(left hand side) detuning direction indicator. When either Q22 or

Q23 is on, the Q24 base voltage will be high, resulting in Q24 being tumed on and Q25 tumed off, which means that the center tuning indicator will not be lit up,

Once the broadcastingfrequency hasbeentuned properly, the voltageson pin nos.2 & 4 will be

equal. Consequently,q22 and Q23 will both be turned off, which meansthat neither of the detun- ing direction indicators will be on in this case.And since Q24 is tumed off becauseof the decreased basevoltage, Q25 will be turned on, and the center tuning indicator light up. Furthermore, C77 is chargedup via R99, resuitingin Q26 beingtumed on, thereby lighting up the Quartz Locked indi- cator LED.

4 . 4 E O U A L I Z E RA M P L I F I E R

?his circuit is an NFB type equalizer amplifier with newly developed high performance IC (HA1201?P) .

This IC is a low-noiseand low distortion type, and provide an openloop gain of 105d8. The main performance specifications for this circuit include a voltage gain of 35.5d8 (at lkHz), a phono dynamic margin or maximum allowableinput level of 250mV (1kHz, 0.}Abc/oTHD), S/N ratio of 82dB (at 2.5mV input, IHF-A), and equalization within t0.2dB (20H2* 20kHz).

4 . 5 T O N EC O N T R O LA M P L I F I E R

This circuit is an NFB type tone control ampli- fier with newly developedhigh performance IC iHA12017P).

4 . 6 P O W E RA M P L I F I E R AmplifierCircuit

The basic circuit arrangement of the power amplifier is shown in Fig. 4-9. The first stageis a differential amplifier comprisingPNP twin transis- tor (Q2), the load circuit of which is a current mirror employing an NPN twin transistor (Q3). The current mirror providespush-pulloperationin this stage,which seruesto cancel even harmonics and further increasegain.

Q1 in the input circuit absorbsoutflorv of base current from Q2, and preventsthe generationof a DC voltage.BecauseQ1 follows any temperature drift in Q2, temperaturedrift of the center point voltageis prevented.

The pre-driver stage (Q4, Qb) is a Darlington arrangement,the load circuit of which employs a constant-currentsource(Q6) resultinga high volt- agegain.

The power stagebias voltageis suppliedby the high speed bias servocontrol circuit. The high speed bias servocontrol circuit provides non- switching operation in the power stage (refer to "High SpeedBiasServocontrolCircuit").

The power stage(Q13 - Q16) is a 2-stageDari- ington arrangement,the last stage is SEPPcircuit employing an SL RET (Super Linearit5'Ring Emitter Transistor).The RET is a kind of IC con- sistingof a number of smail transistorson a single chip, with each transistor being connected ir"r parallel via an emitter resistor. This provides

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Fig . 4 - 9 Poweramplifier

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