Video Mode Timing—AMLCD Video Mode, QVGA, Fixed
Item Description Min. Max. Units
1 HS low time 2 200 VCLK periods
2 HS to VCLK phase difference 10 VCLK period - 10 nsec
5 VCLK frequency 7 MHz
6 R/G data set up to VCLK 5 nsec
7 R/G data hold from VCLK 10 nsec
8 VS low width 2 34 HS periods
9 VS to HS phase difference 0 HS period – HS low
time
nsec
10 Vertical start position After 7 HS rising edges
HS period 50 usec
VS period 251 280 HS periods
HS
VCLK
R/G dat
a
VS
HS
Horizontal Timing
Vert ical Timin
g
data for f irst p ix e l
9
8
6 7
5
10
1
horizontal invalid dat a period
clock edge C1 first valid clock =
clock edge C52
R/G dat
a
vertical in v a lid d a ta p e rio d
data for f irst lin e
Line 1 Line 2 Li ne N
2
EL320.240-FA3 Operations Manual Page 17 of 25