Planar EL552.256-Q2 manual Self-Test Mode, Pixel Location vs. Sequence of Data

EL552.256-Q2

Input signals VID0 through VID3 contain the video data for the screen. As shown in Figure 4, pixel information is supplied from left to right and from top to bottom, four pixels at a time. Video data for one row is latched on the fall of HS.

1,2,3,4

5,6,7,8

9,10,11,12 13,14,15,16

549, 550, 551, 552

Row 1

EL Panel

(Front)

VID3	1	5	9	13
VID2	2	6	10	14
VID1	3	7	11	15
VID0	4	8	12	16

Figure 4. Pixel Location vs. Sequence of Data

549

550

551

552

Self-Test Mode

The display will enter the self-test mode if all seven video inputs (VCLK, HS, VS, and VID0 through VID3) are high for longer then 2.5 seconds at power up. The self-test scans at 100 Hz with a diagonal pattern that changes back and forth every 2.5 seconds from 3 pixels on/1 pixel off to 1 pixel on/3 pixels off.

After the self-test, turn the display off and wait at least 15 seconds before reapplying power to allow the internal capacitors to completely discharge. When you turn the display on again, apply video signals in less than 2.5 seconds after power up to enter normal operation.

8EL552.256-Q2 Operations Manual (OM410-00)