PMC-Sierra PM7347 manual S/Uni-Jet, SATURN User Network Interface for J2/E3/T3, Features

	PMC-Sierra,Inc.	PM7347
		S/UNI-JET
SATURN User Network Interface for J2/E3/T3

FEATURES

•Single-chip ATM User Network Interface (UNI) operating at 44.736 Mbit/s, 34.368 Mbit/s, and 6.312 Mbit/s conforming to ATMF-95-1207R1, ATMF-94-0406R5, and AF-PHY-0029.000.

•Provides on-chip DS3, E3 (G.751 and G.832), and J2 framers. Can be configured for use solely as a framer. When configured in framer mode, gapped transmit and receive clocks can be generated for interfaces that need access only to payload data bits.

•Supports bypass of the internal framers and supports connections to an arbitrary-rate external transmission system interface up to a rate of 52 Mbit/s. This lets the S/UNI-JET be used as an ATM cell delineator.

•Implements ATM direct-cell mapping into T1, DS3, E1, E3, and J2 transmission systems according to ITU-T Recommendation G.804.

•Provides a SCI-PHY and 50 MHz UTOPIA Level 2 compatible 8- or 16-bit ATM-PHY Interface.

•Implements the Physical Layer Convergence Protocol (PLCP) for T1 and DS3 transmission systems according to the ATM Forum UNI Specification and ANSI TA-TSY-000773, TA-TSY-000772, and for E1 and E3 transmission systems according to ETSI 300-269 and ETSI 300-270.

•Implements the ATM physical layer for broadband ISDN according to ITU-T Recommendation I.432.

•Uses the PM4341 T1XC, PM6341 E1XC, PM4351 COMET, and framer/ line interface chips for T1 and E1 applications.

•Provides seamless interface to the VORTEX DSLAM chipset, S/UNI®-ATLAS, and S/UNI-RCMP-200.

•Provides programmable pseudo-random test pattern generation, detection, and analysis features.

•Provides integral transmit and receive HDLC controllers with 128-byte FIFO depths.

•Provides performance monitoring counters suitable for accumulation periods up to one second.

•Provides an 8-bit microprocessor interface for configuration, control, and status monitoring.

•Provides a standard 5-signal P1149.1 JTAG test port for boundary scan board-test purposes.

•Low power 3.3 V CMOS technology with 5 V-tolerant inputs.

•Available in a high density 256-pin SBGA package (27 mm by 27 mm).

•Rated for industrial temperature operation.

APPLICATIONS

•DSLAM Uplinks

•Enterprise ATM/PPP Uplinks

•ATM or Frame Relay Switches, Multiplexers, and Routers

•DS3/E3/J2 PPP Internet Access Interfaces

•DS3/E3/J2 Frame Relay Interfaces

BLOCK DIAGRAM

SIG T1: TPOHINS
SIG T2: TPOH/TDAT
SIG T3: TIOHM/TFP/TMFP
SIG T4: TICLK
SIG T5: TPOHCLK
SIG T6: TPOHFP/TFPO/TMFPO/TGAPCLK/TCELL
SIG T7: REF8KI					TOH TOHINS		TOHFP TOHCLK
	XBOC		TDFR			Transmit		1/2 TTB
								Transmit
	Receive	Receive
				TRAN

SIG	SIG	SIG	SIG	SIG	SIG	SIG
T1	T2	T3	T4	T5	T6	T7

SPLT

TDOTCKTDITMSTRSTB

IEEE

P1149.1

DTCA

TDAT [15:0]

TPRTY

TNEG/TOHM		Line		J2, E3 OR DS3
TPOS/TDATO
TCLK
RCLK
		Line			FRMR
RPOS/RDAT				J2, E3 or DS3
RNEG/RLCV/ROHM
	RBOC		RFDL		PMON	Receive		1/2 TTB
	Receive		Receive		Perfor-		O/H	Receive
					mance

Transmit

ATM and

PLCP

Framer

ATMF/SPLR

Receive

ATM and

PLCP

Framer

PRGD BER

CCPM

PLCP/cell

TXCP_50

Transmit

RXCP_50

Receive

TXFF

Transmit

RXFF

Receive

4-Cell

MPIF

Microprocessor

System

TSOC

TCA

TADR [2:0]

TENB

TFCLK

PHY_ADR[2:0]

ATM8

RFCLK

RENB

RADR [2:0]

RCA

RSOC

RPRTY RDAT [15:0]

DRCA

SIG R1: FRMSTAT

SIG R2: RPOCHCLK/ RSCLK/RGAPCLK SIG R3: REF8KO/

RPOHFP/RFPO/RMFPO SIG R4: RPOH/ROVRHD SIG R5: LCD/RDATO

ROHCLK ROH	ROHFP					RCELL	D[7:0]	INTB RSTB RDB WRB CSB ALE A[10:0]
		SIG	SIG	SIG	SIG SIG
		R5	R4	R3	R1 R2

PMC-990996 (R2) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ￿ 1999 PMC-Sierra, Inc.