Premio Computer Premio Apollo/Shadowhawk Computer Rdram Bus Frequency, Dram Data Integrity Mode

CHAPTER 4 AWARD® BIOS SETUP

RDRAM Bus Frequency

This will show the RDRAM Bus Frequency during boot-up. The settings are Auto, 400MHz and 300MHz.

DRAM Data Integrity Mode

This option allows you to select the Parity or ECC (Error-Checking and Correcting), according to the type of installed DRAM.

System BIOS Cacheable

Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in better system performance. However, if any program writes to this memory area, a system error may result. The settings are: Enabled and Disabled.

Video BIOS Cacheable

Select Enabled allows caching of the video BIOS , resulting in better system performance. However, if any program writes to this memory area, a system error may result. The settings are: Enabled and Disabled.

Memory Hole At 15M-16M

You can reserve this area of system memory for ISA adapter ROM. When this area is reserved, it cannot be cached. The user information of peripherals that need to use this area of system memory usually discusses their memory requirements. The settings are: Enabled and Disabled.

Delayed Transaction

The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles. Select Enabled to support compliance with PCI specification version 2.1. The settings are Enabled and Disabled.

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