D1 -RXSRC, RECEIVE DMA SOURCE:
When set (logic 1), this bit allows the source for Receive DMA to come from the
W/REQB pin of channel B on the SCC. When cleared (logic 0), the source for Receive DMA
comes from the W/REQA pin of channel A on the SCC.
D0 -TXSRC, TRANSMIT DMA SOURCE:
When set (logic 1), this bit allows the source for Transmit DMA to come from the
DTR/REQA pin of channel A on the SCC. When cleared (logic 0), the source for Transmit DMA
comes from the W/REQA pin of channel A of the SCC.
NOTE:
Even though the W/REQA pin can be used for both DMA transmit
and DMA receive, obviously it cannot be used for both
simultaneously. Therefore, bits D0 and D1 of the Configuration
Register should never be cleared at the same time while bits D2 and
D3 are both set. This situation may result in damage to the system.
MPA-100 User's Manual 8-2