7.4. Register Operation Limitations

7.4. Register Operation Limitations

Table 6-2 lists the limitations on register operation. The registers are inhibited from any modification. If register contents are modified in any way, kernel operation cannot be guaranteed.

Table 7-2: Limitations on Register Operation

Register Name

Restriction

User and Interrupt Stack Pointers

RAM memory range 0B80H – 0BFFH is used by

 

the kernel. Do not set stacks in this area.

UART1 Transmit/Receive Mode Register

Do not change.

UART1 Transmit/Receive Control Register 0

 

UART1 Transmit/Receive Control Register 1

 

UART1 Interrupt Control Register 0

Do not change.

UART Transmit/Receive Control Register 2

Do not change bits 0 and 2.

UART1 Transmit Buffer Register

Do not write to this register.

UART1 Receive Buffer Register

Do not read this register.

Port 6 and Port 6 DDR

To prevent changes on P6_4 data and direction,

 

use read-modify-write only instructions (BSET,

 

BCLR, AND, OR, etc.).

7.5. Limitations on Interrupts – Vectors that Reside in the Hardware Vector Table

Table 7-3lists the limitations on hardware interrupt (i.e. fixed) vector addresses.

Table 7-3: Interrupt Vector Addresses

Interrupt Cause

M16C/26A Vector Address

Kit Specification

Undefined

FFFDCh ~ FFFDFh

User available

Overflow

FFFE0h ~ FFFE3h

User available

BRK Instruction

FFFE4h ~ FFFE7h

User inhibited

Address Match

FFFE8h ~ FFFEBh

User inhibited

Single-step

FFFECh ~ FFFEFh

User inhibited

Watchdog Timer

FFFF0h ~ FFFF3h

User available (Note 1)

DBC

FFFF4h ~ FFFF7h

User inhibited

NMI

FFFF8h ~ FFFFBh

User available

RESET

FFFFCh ~ FFFFFh

Reset vector (Note 2)

NOTES:

(1)The Watchdog Timer vector is shared with the oscillation stop and voltage detection interrupts. The vector is available for oscillation stop and voltage detection interrupts, but you must avoid using the vector for watchdog timer interrupts.

(2)The kernel transparently relocates the Reset vector to FFFD8h.

7.6.Stop or Wait Mode Limitations

The kernel cannot be run in STOP or WAIT modes. Do not use these modes when debugging your program.

7.7. User Program’s Real-Time Capability (Very Important – Please Read)

Please be aware that while the kernel is in a “STOP” state, the hardware peripherals will continue to run. Therefore, interrupts may not be serviced properly. In addition, the watchdog timer will not be serviced and will likely time out if active.

HTS Demo Kit V1.0

12/ 20

December 2007

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Renesas HEW Target Register Operation Limitations, Stop or Wait Mode Limitations, 2 Limitations on Register Operation