Sanyo EP58B specifications LC74152B, LC74186E

Digital TV TS + Audio + Video Decoder IC with Built-in OSD Function

LC74152B

Overview

The LC74152B is a digital TV decoder IC that integrates MPEG2 video decoder, AAC audio decoder, transport stream decoder, data broadcast OSD, video scaler, and NTSC encoder functions on the same chip.

The video decoder down decodes the HDTV stream to 480i/480p. The digital TV backend block can be implemented by combining this IC with a system controller (CPU).

Digital TV 32-Bit RISC Microcontroller

LC74186E

Overview

The LC74186E is 32-bit microcontroller for digital TV that uses the IBM PowerPC R as its CPU core and integrates on a single chip a wide range of peripheral functions, including UART, I2C bus control, timer, synchronous serial port, parallel port, external SDRAM control, and external bus control functions.

✽: The following are trademarks of International Business Machines Corporation in the

Unaited States,or other countries,or both. IBM,PowerPC R

Functions

[TS Decoder Block]

Supports two TS channel inputs

8-bit parallel TS inputs

Either internal or external synchronization can be selected Supports up to 55 indexes. The PID and channel number can be set for each index.

[Video Decoder Block]

Down decodes the HD stream to 480i/480p Supports two-channel HD down decoded playback,

two-channel HD down decoded plus 480p normal playback, and three-channel 480p normal playback

[OSD Block]

Supports both 480i and 480p display

Supports both the 16 bits per pixel YUV 422 format and the 8 bits per pixel CLUT8 format

[Scaler Block]

Two scalers are provided, supporting two-screen structures or video recording output

Supports satellite broadcast multi-view 3-screen display

[Encoder Block]

NTSC interlaced encoding

Can generate two video output systems

Functions

[IBM PowerPC R (PPC405D4)]

Operation at clock frequencies up to 216 MHz

16 KB instruction cache 16 KB data cache

[External SDRAM Control] 32-bit data bus

Support for two logical banks (two chip select signals) Support for 4 MB to 256 MB per logical port

[External Bus Control]

Up to 8 ROM, EPROM, SRAM, flash, and slave peripheral

SCP (synchronous serial port): 1 channel

UART: 3 channels

I2C bus controller: 1 channel (I2C)

Smart Card interface: 1 channel

General-purpose timer (GPT)

General-purpose parallel port (GPIO)

Interrupt controller (UIC)

DMA controller (DMAC)

System clock generator PLL circuit

Supply voltage: 3.3 V

Package: PQFP208 (0.5 mm lead pitch, 28 mm square)

[Audio Decoder Block]

MPEG AAC 5.1 channel decoding (with the output mixed	Supply voltage: 1.8 V (internal), 3.3 V (I/O)
down to two channels)	Package: PBGA352 (35 35)
MPEG BC decoding

			Block Diagram
		SDRAM	SDRAM
		(32bit 2M)	(32bit	2M)
27MHz
		Arbiter
Host CPU	CPUIF
				SCALER	16-bit digital video interface
TSIN1					(SD input, main output)
	TS				8-bit digital video interface
TSIN2					(Recording output)
				OSD with
TSOUT				ISDB support
	VIDEO
				VDAC	Three analog video channels
				NTSC encoder	(Main outputs: Y.Pb.Pr/Y.C)
	AUDIO			VDAC	Three analog video channels
					(Subsidiary output
					: Y/C composite video)
	DAC I/F	DIT(PCM&encoded stream)
	(Main output: video recording output)

I/O banks (8 CS signals)

Support for both burst and non-burst transfer devices 26-bit address bus, 16-bit data bus

				Block Diagram
		ROM/SRAM control	SDRAM control	DMA control
					OPB
		ROM/SRAM	SDRAM	DMA	Parallel port	Parallel port
		external	controller	controller
		bus controller
					General-purpose timer	Timer I/O
	Arbiter			PLB
					Smart Card interface	Smart Card control
				PLB/OPB
		Instruction	Data	bridge	Asynchronous serial port	Asynchronous serial port
		cache	cache
		16KB	16KB		Synchronous serial port	Synchronous 3-wire
						serial port
		Memory management unit			I2C bus controller	I2C bus control
Debugging	JTAG
		Execution unit
interface	port
		Time
				Interrupt		Interrupt input
	PPC405core			controller
					Clock generator
						Clock inpu
					PLL

5 SANYO TV . VCR SANYO TV . VCR 6