Appendix A.AT interface connector pin assignments
Reset–
Ground
DD7
DD8
DD6
DD9
DD5
DD10
DD4
DD11
DD3
DD12
DD2
DD13
DD1
DD14
DD0
DD15
Ground
(removed)
DMARQ
Ground
DIOW–
Ground
DIOR–
Ground
IORDY
SPSYNC:CSEL
DMACK–
Ground
INTRQ
IOCS16–
DA1
PDIAG–
DA0
DA2
CS1FX–
CS3FX–
DASP–
Ground
*Indicates master-slave signals (details shown below).
Host
28
34
39
Drive 0
(master)
Drive 1
(slave)
28
34
39
28
34
39
SPSYNC:CSEL
PDIAG–
DASP–
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Host Reset
Ground
Host Data Bus Bit 7
Host Data Bus Bit 8
Host Data Bus Bit 6
Host Data Bus Bit 9
Host Data Bus Bit 5
Host Data Bus Bit 10
Host Data Bus Bit 4
Host Data Bus Bit 11
Host Data Bus Bit 3
Host Data Bus Bit 12
Host Data Bus Bit 2
Host Data Bus Bit 13
Host Data Bus Bit 1
Host Data Bus Bit 14
Host Data Bus Bit 0
Host Data Bus Bit 15
Ground
(No Pin)
DMA Request
Ground
Host I/O Write
Ground
Host I/O Read
Ground
I/O Channel Ready
Spindle sync
or Cable Select
DMA Acknowledge
Ground
Host Interrupt Request
Host 16 Bit I/O
Host Address Bus Bit 1
Passed Diagnostics
Host Address Bus Bit 0
Host Address Bus Bit 2
Host Chip Select 0
Host Chip Select 1
Drive Active/
Drive 1 Present
Ground
Host pin # and signal description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
*28
29
30
31
32
33
*34
35
36
37
38
*39
40
Drive pin # Signal name

ST9100A and ST9100AG Installation Guide, Rev. A 11