AN.No.G1216B1N000-3D0E
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2.2.1 Block Diagram (Segment Driver)
Input and Output Buffer
Instruction Register
X, Y-Address
Counter
Z-Address
Counter
Display Start Line
Register
Busy Flag
Display Data RAM
4096 bit
CS R/W D/I DB0 to DB7
E
LC Driver
Display ON/OFF
M
FRM CL1
RST
Input
Register
Output
Register
Display Data Latch
Segment Driver
VDD VSS VLC
8
6
Interface Control
4
Va
Vc
Vd
Vf
64
64
8
8
8
8
9
9
6
6
Y1 Y2 Y64
2
Fi
g
ure 3 Se
g
ment Driver