SDRAM Block ( Standard & Option ) |
|
| |
=?%+4%7+6&+#)4#/HO!"#!$ |
| OSC | |
| X3 | ||
| 66.666Mhz | ||
|
| ||
|
| DRCLK | Clock |
|
|
| |
|
| MEMCLK0 | buffer |
|
| IC9 | |
| MAA[12:0] |
|
|
| MD[63:0] | SDRAM |
|
|
|
| |
| SDQMA[7:0] |
|
|
| MWE | IC4, 5,6,7 |
|
|
|
| |
| MCS0 | 128Mbit x 4 |
|
| MRASA |
| |
| MCASA |
|
|
System | BSEL0A,1A |
|
|
CKEA |
|
| |
Controller |
|
| |
|
|
| |
IC19 |
|
|
|
456pin- |
|
|
|
BGA |
| MEMCLK1,2,3,4 | |
| MWE | DIMM Slot |
|
|
|
| |
| MCS1A,2A | CN3 |
|
| MRASA |
| |
| (64,128,256MB) |
| |
| MCASA |
| |
|
|
| |
| BSEL0A,1A |
|
|
| CKEA |
|
|
| SDA,SCL |
|
|
|
| ||
