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| USB Hub with Integrated 10/100 Ethernet Controller | |
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| Datasheet |
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| Table 2.1 EEPROM Pins |
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NUM |
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| BUFFER |
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PINS | NAME | SYMBOL |
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| DESCRIPTION | |
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1 |
| EEPROM Data | EEDI |
| IS | This pin is driven by the EEDO output of the | |
| In |
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| (PD) | external EEPROM. | ||
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1 |
| EEPROM Data | EEDO |
| O8 | This pin drives the EEDI input of the external | |
| Out |
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| EEPROM. | ||
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1 |
| EEPROM Chip | EECS |
| O8 | This pin drives the chip select output of the external | |
| Select |
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| EEPROM. | ||
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| EEPROM Clock | EECLK |
| O8 | This pin drives the EEPROM clock of the external | |
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| EEPROM. | ||
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| Table 2.2 JTAG Pins |
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NUM |
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PINS | NAME | SYMBOL |
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| JTAG Test Port | nTRST |
| IS | This active low pin functions as the JTAG test port | |
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| Reset |
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| reset input. | |
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| Note: | This pin should be tied high if it is not | |
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| used. |
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1 |
| JTAG Test | TMS |
| IS | This pin functions as the JTAG test mode select. | |
| Mode Select |
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1 |
| JTAG Test Data | TDI |
| IS | This pin functions as the JTAG data input. | |
| Input |
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1 |
| JTAG Test Data | TDO |
| O12 | This pin functions as the JTAG data output. | |
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| JTAG Test | TCK |
| IS | This pin functions as the JTAG test clock. The | |
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| Clock |
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| maximum operating frequency of this clock is | |
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| 25MHz. |
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| Table 2.3 Miscellaneous Pins | ||||
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NUM |
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PINS | NAME | SYMBOL |
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| System Reset | nRESET |
| IS | This active low pin allows external hardware to | |
1 |
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| reset the device. | |
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| Note: | This pin should be tied high if it is not | |
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| used. |
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| Ethernet | nFDX_LED |
| OD12 | This pin is driven low (LED on) when the Ethernet | |
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| (PU) | link is operating in | ||
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| Indicator LED |
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| General | GPIO0 |
| IS/O12/ | This General Purpose I/O pin is fully programmable | ||
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| Purpose I/O 0 |
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| OD12 | as either a | |
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| (PU) | or a | |
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Revision 1.0 | 10 | SMSC LAN9512 |
| DATASHEET |
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