USB Hub with Integrated 10/100 Ethernet Controller

 

 

 

 

 

 

 

Datasheet

 

 

 

 

Table 2.1 EEPROM Pins

 

 

 

 

 

 

 

 

 

NUM

 

 

 

BUFFER

 

 

PINS

NAME

SYMBOL

 

TYPE

 

DESCRIPTION

 

 

 

 

 

 

 

1

 

EEPROM Data

EEDI

 

IS

This pin is driven by the EEDO output of the

 

In

 

 

(PD)

external EEPROM.

 

 

 

 

 

 

 

 

 

 

 

1

 

EEPROM Data

EEDO

 

O8

This pin drives the EEDI input of the external

 

Out

 

 

 

EEPROM.

 

 

 

 

 

 

 

 

 

 

 

 

1

 

EEPROM Chip

EECS

 

O8

This pin drives the chip select output of the external

 

Select

 

 

 

EEPROM.

 

 

 

 

 

 

 

 

 

 

 

 

1

 

EEPROM Clock

EECLK

 

O8

This pin drives the EEPROM clock of the external

 

 

 

 

 

EEPROM.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 2.2 JTAG Pins

 

 

 

 

 

 

 

 

 

NUM

 

 

 

BUFFER

 

 

PINS

NAME

SYMBOL

 

TYPE

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

JTAG Test Port

nTRST

 

IS

This active low pin functions as the JTAG test port

1

 

Reset

 

 

 

reset input.

 

 

 

 

 

Note:

This pin should be tied high if it is not

 

 

 

 

 

 

 

 

 

 

 

 

 

used.

 

 

 

 

 

 

 

1

 

JTAG Test

TMS

 

IS

This pin functions as the JTAG test mode select.

 

Mode Select

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

JTAG Test Data

TDI

 

IS

This pin functions as the JTAG data input.

 

Input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

JTAG Test Data

TDO

 

O12

This pin functions as the JTAG data output.

 

Out

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JTAG Test

TCK

 

IS

This pin functions as the JTAG test clock. The

1

 

Clock

 

 

 

maximum operating frequency of this clock is

 

 

 

 

 

 

25MHz.

 

 

 

 

 

 

 

 

 

 

Table 2.3 Miscellaneous Pins

 

 

 

 

 

 

 

 

NUM

 

 

 

BUFFER

 

 

PINS

NAME

SYMBOL

 

TYPE

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

System Reset

nRESET

 

IS

This active low pin allows external hardware to

1

 

 

 

 

 

reset the device.

 

 

 

 

 

Note:

This pin should be tied high if it is not

 

 

 

 

 

 

 

 

 

 

 

 

 

used.

 

 

 

 

 

 

 

 

 

Ethernet

nFDX_LED

 

OD12

This pin is driven low (LED on) when the Ethernet

 

 

Full-Duplex

 

 

(PU)

link is operating in full-duplex mode.

1

 

Indicator LED

 

 

 

 

 

 

General

GPIO0

 

IS/O12/

This General Purpose I/O pin is fully programmable

 

 

 

 

 

Purpose I/O 0

 

 

OD12

as either a push-pull output, an open-drain output,

 

 

 

 

 

(PU)

or a Schmitt-triggered input.

 

 

 

 

 

 

 

 

Revision 1.0 (04-20-09)

10

SMSC LAN9512

 

DATASHEET