Desktop System Controller Hub with Advanced, 8051µC-Based Auto Fan Control

General Description

The SCH5617C is a 3.3V PC 2001 compliant Super I/O controller with an LPC interface. All legacy drivers used for Super I/O components are supported making this interface transparent to the supporting software. The LPC bus also supports power management, such as wake-up and sleep modes.

The SCH5617C provides temperature monitoring with auto fan control. The temperature monitor is capable of monitoring two external diodes, one internal ambient temperature sensor or retrieving temperatures from external processors that implement the PECI Interface. This includes support for the PECI REQUEST# and PECI AVAILABLE signals that are used to assure correct operation of PECI when processors enter the C3/C4 sleep states. This device offers programmable automatic fan control support based on one or more of these measured temperatures. There are three pulse width modulation (PWM) outputs with high frequency support as well as three fan tachometer inputs. In addition, there is support for a PROCHOT_IN# pin that may be used to generate an interrupt, adjust the programmed temperature limits in the auto fan control logic, or force the PWM outputs on full. There is also a separate PROCHOT_OUT output pin.

The GLUE Logic includes various power management logic including generation of RSMRST# and Power OK signal generation. There are also four LEDs to indicate power status and hard drive activity. Also included is SMBus Isolation logic, which can be used to isolate SMBus signals during power down modes.

The part provides 45 General Purpose I/O control pins, which offer flexibility to the system designer. There are 21 Scratchpad read/write runtime registers for custom use.

The SCH5617C incorporates the following Super I/O components: a parallel port that is compatible with IBM PC/AT architecture, as well as the IEEE 1284 EPP and ECP; two serial ports that are 16C550A UART compatible; a keyboard/mouse controller that uses an 8042 micro controller; two floppy controllers, which use SMSC's true CMOS 765B core; one infrared port that is IrDA 1.0 compliant. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures and is software and register compatible with SMSC's proprietary 82077AA core. The part also provides a low battery warning circuit.

The SCH5617C is ACPI 1.0b/2.0 compatible supports multiple low power-down modes. It incorporates sophisticated power control circuitry (PCC), which includes keyboard and mouse wake-up events.

The SCH5617C supports the ISA Plug-and-Play Standard register set (Version 1.0a). The I/O Address, DMA Channel and hardware IRQ of each logical device in the SCH5617C may be reprogrammed through the internal configuration registers. There are up to 480 (960 for Standard Mode Parallel Port) I/O address location options, a Serialized IRQ interface, and four DMA channels.

SMSC SCH5617C

PRODUCT3 PREVIEW

Revision 0.7 (12-09-08)