
Datasheet
Chapter 7 Functional Overview
Figure 2.1 shows the functional block diagram of the USB 2.0 Hub Controller. Each of the functions is described in detail below.
7.1Bus-Power Detect
The VBUSDET pin on the USB20H04 monitors the state of the upstream VBUS signal and will not
USB20H04 will remove power from the DP0
To support a
7.2Upstream PHY
The upstream PHY includes the transmitter and receiver that operate in
To support a
7.3Clock/PLL
The USB20H04 requires a 24MHz signal as a reference clock for the internal PLL. An external crystal is used with the internal oscillator, or an external clock signal can be provided.
7.4Internal Configuration Select
A default configuration for the USB20H04 is present immediately after RESET_N negation. When the default configuration values will not be used, user defined values must be provided from an external source via the serial interface. The user defined values to be configured are described in section 8.2.
See Section 8.1 for typical circuit examples showing how to select either the default configuration or an external EEPROM. The pins used to select the source of configuration values are given in Table 4.2.
The internal default configuration is enabled when SMB_SEL_N is high and CS/EE_SEL is low on the rising edge of RESET_N. When the SELF_PWR pin is low on the rising edge of RESET_N, the
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