SMSC USB20H04 Chapter 7 Functional Overview, 7.1Bus-PowerDetect, 7.2Upstream PHY, 7.3Clock/PLL, 7.4Internal Configuration Select

4-Port USB 2.0 Hub Controller

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Chapter 7 Functional Overview

Figure 2.1 shows the functional block diagram of the USB 2.0 Hub Controller. Each of the functions is described in detail below.

7.1Bus-Power Detect

The VBUSDET pin on the USB20H04 monitors the state of the upstream VBUS signal and will not pull-up the DP0 resistor if VBUS is not active. If VBUS goes from an active to an inactive state (not powered), the

USB20H04 will remove power from the DP0 pull-up resistor within 10 seconds.

To support a dual-role OTG host on the upstream port, the USB20H04 has the ability to pulse the inactive VBUS line. This is defined as VBUS pulsing in the OTG specification. For a more detailed discussion of the OTG features of the USB20H04, please see “Application Note 10.4 Using the USB20H04 with an OTG Host”.

7.2Upstream PHY

The upstream PHY includes the transmitter and receiver that operate in high-speed or full-speed mode, depending on the current hub configuration and the host. The required termination resistors are internal to the USB20H04.

To support a dual-role OTG host on the upstream port, the USB20H04 has the ability to attach a 1.5K ohm resistor to the DP0 pin for 5 to 10ms. This is defined as data-line pulsing in the OTG specification.

7.3Clock/PLL

The USB20H04 requires a 24MHz signal as a reference clock for the internal PLL. An external crystal is used with the internal oscillator, or an external clock signal can be provided.

7.4Internal Configuration Select

A default configuration for the USB20H04 is present immediately after RESET_N negation. When the default configuration values will not be used, user defined values must be provided from an external source via the serial interface. The user defined values to be configured are described in section 8.2.

See Section 8.1 for typical circuit examples showing how to select either the default configuration or an external EEPROM. The pins used to select the source of configuration values are given in Table 4.2.

The internal default configuration is enabled when SMB_SEL_N is high and CS/EE_SEL is low on the rising edge of RESET_N. When the SELF_PWR pin is low on the rising edge of RESET_N, the bus-powered default configuration is loaded. If the SELF_PWR pin is high, the self-powered default configuration is loaded. This allows the default configuration to be bus-powered or self-powered following a reset.

Revision 1.63 (03-30-07) Page 16 SMSC USB20H04

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