Sony CMD-J5/J16 specifications Block Diagram Baseband, General Baseband Indications

6.2 Block Diagram - Baseband

MCP-I/F BL-I/F

FLASH/SRAM

KEY-I/F

LCD-I/F

LCD

IC 1

I/O CONNECTOR

1DGND

2	CHG	MODEM -I/F	JOG-I/F
3
	GEN I/O

4POWER OUT

5	RX (IN)	TIME
6	TX (OUT)	PROCCESSING		AUDIO
		UNIT
7	ACC ID			AMP
8	RTS	RTC	32kHz
9	CTS			RF-I/F
			CLK-
10	AUDIO OUT		CTRL
		SIM
11	AUDIO IN
12	AGND	Interface	IC 2
			I/F
Battery			IC 1
Connector		Power / CHG	I/F

KEY-LED

LCD-LED

KEY-MATRIX

KEYBOARD

JOG

RINGER

HEADSET

AUDIO &

REMOTE

MIC

FLEX-BOARD

SLIDE-SW (REC/LOCK or Manner)

JOG DIAL

Multiactor

*Ringer

*Vibrator *Loud- Speaker

HEADPHONE-JACK

Management

LI-ION
BATTERY	SIM I/F	AUDIO
		I/F

RTC / ID HFK I/F IC 2

SIM	SIM LEVEL
	CTRL 3V/5V
Connector

A/D CONV RF I/F A/D, D/A

SIM CARD

RF TCXO

BLOCK

AUDIO	EAR
AMP
	RECEIVER

MIC

6.2.1 General Baseband Indications

The Baseband part consists of two chips, a digital chip IC 1 and an analog one IC 2. The CMD-J5/J16 external memory size is 32 Mbits Flash ROM and 4 Mbit SRAM.

IC 1

The application of IC 1 is the management of the GSM baseband processes through the GSM layer 1, 2 and 3 protocols as described in the ETSI standard with a specific attention to the power consumption in both GSM dedicated and idle modes.

It is a chip that implements:

the digital baseband processes of the CMD-J5/J16 and combines a Digital Signal Processing (DSP) with its program and data memories,

a Micro-Controller core with emulation facilities and an internal RAM memory, a clock squarer cell,

several compiled ports and equivalent CMOS gates.

Full support for Full-Rate, Enhanced Full-Rate and Half-Rate speech coding is given.

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