Sony MDX-C6500RV service manual Ic Pin Function Description, SERVO BOARD IC301 CXD2652AR

4-19. IC PIN FUNCTION DESCRIPTION

•SERVO BOARD IC301 CXD2652AR

(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, EFM/ACIRC ENCODER/DECODER, SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER, 2M BIT D-RAM)

Pin No.	Pin Name	I/O		Description
1	MNT0	O	Focus OK signal output to the MD mechanism controller (IC501)
			“H” is output when focus is on (“L”: NG)
2	MNT1	O	Track jump detection signal output to the MD mechanism controller (IC501)
3	MNT2	O	Busy monitor signal output to the MD mechanism controller (IC501)
4	MNT3	O	Spindle servo lock status monitor signal output to the MD mechanism controller (IC501)
5	SWDT	I	Writing serial data signal input from the MD mechanism controller (IC501)
6	SCLK	I	Serial data transfer clock signal input from the MD mechanism controller (IC501)
7	XLAT	I	Serial data latch pulse signal input from the MD mechanism controller (IC501)
8	SRDT	O (3)	Reading serial data signal output to the MD mechanism controller (IC501)
9	SENS	O (3)	Internal status (SENSE) output to the MD mechanism controller (IC501)
10	XRST	I	Reset signal input from the MD mechanism controller (IC501) “L”: reset
11	SQSY	O	Subcode Q sync (SCOR) output to the MD mechanism controller (IC501)
			“L” is output every 13.3 msec	Almost all, “H” is output
12	DQSY	O	Digital In U-bit CD format subcode Q sync (SCOR) output terminal
			“L” is output every 13.3 msec	Almost all, “H” is output				Not used (open)
13	RECP	I	Laser power selection signal input terminal
			“L”: playback mode, “H”: recording mode (fixed at “L” in this set)
14	XINT	O	Interrupt status output to the MD mechanism controller (IC501)
			Recording data output enable signal input terminal
15	TX	I	Writing data transmission timing input (Also serves as the magnetic head on/off output)
			Not used (fixed at “L”)
16	OSCI	I	System clock signal (512Fs=22.5792 MHz) input from the oscillator circuit
17	OSCO	O	System clock signal (512Fs=22.5792 MHz) output terminal					Not used (open)
18	XTSL	I	Input terminal for the system clock frequency setting
			“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)
19	RVDD	—	Power supply terminal (+3.3V) (digital system)
20	RVSS	—	Ground terminal (digital system)
21	DIN	I	Digital audio signal input terminal when recording mode				Not used (fixed at “L”)
22	DOUT	O	Digital audio signal output terminal when playback mode				Not used (open)
23	ADDT	I	Recording data input terminal	Not used (fixed at “L”)
24	DADT	O	Playback data output to the PCM1718E (IC101)
25	LRCK	O	L/R sampling clock signal (44.1 kHz) output to the PCM1718E (IC101)
26	XBCK	O	Bit clock signal (2.8224 MHz) output to the PCM1718E (IC101)
27	FS256	O	Clock signal (11.2896 MHz) output to the PCM1718E (IC101)
28	DVDD	—	Power supply terminal (+3.3V) (digital system)
29 to 32	A03 to A00	O	Address signal output to the D-RAM (IC307)
33	A10	O	Address signal output to the external D-RAM		Not used (open)
34 to 38	A04 to A08	O	Address signal output to the D-RAM (IC307)
39	A11	O	Address signal output to the external D-RAM		Not used (open)
40	DVSS	—	Ground terminal (digital system)
41	XOE	O	Output enable signal output to the D-RAM (IC307)			“L” active
42	XCAS	O	Column address strobe signal output to the D-RAM (IC307)					“L” active
43	A09	O	Address signal output to the D-RAM (IC307)
44	XRAS	O	Row address strobe signal output to the D-RAM (IC307)				“L” active
45	XWE	O	Write enable signal output to the D-RAM (IC307)			“L” active

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