Sony STR-DE835 specifications 55, Pin No, Pin Name, Description

Pin No.	Pin Name	I/O	Description
31	RIN–	I	Rch analog negative input pin
32	RIN+	I	Rch analog positive input pin
33	VREFL	I	Negative voltage reference input pin, AVSS (Connected to ground)
34	VCOM	O	Common voltage output pin, AVDD/2
			Large external capacitor is used to reduce power-supply noise
35	VREFH	I	Positive voltage reference input pin, AVDD
36	A. 5V	—	Analog power supply pin
37	A. GND	—	Analog ground pin
38	XTI	I	X’tal input pin (Not used)
39	MCLKI	I	External master clock input pin if XTS = “L”
40	S/P	I	Parallel/serial select pin
			“L”: serial control mode, “H”: parallel control mode (Connected to ground)
41	CS	I	Chip select pin in serial mode
42	CCLK	I	Control data clock pin in serial mode
43	CDTI	I	Control data input in serial mode
44	CDTO	O	Control data output pin in serial mode

If pins TEST, ICKS0, ICKS1, PD, S/P, DFS, DEM0, DEM1, CAD0, CAD1, S/M, MCLK, SDOS are not driven, then TEST, ICKS0, ICKS1, CAD0, CAD1, must be tied to either AVSS or AVDD. PD, S/P, DFS, DEM0, DEM1, S/M, MCLK, SDOS must be tied to either DVSS or DVDD.

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