Sony STR-DE835 specifications Pin No, Pin Name, Description

Pin No.	Pin Name	I/O		Description
91	VSS0	—	Ground
92 – 94	EA13 – EA15	O	External RAM address output
95	EA16	O	Not used
96	TSTA	I	Test data input “L” = normal	“H” = test (Connecting to ground)
97	PLDIVF	I	PLL input frequency select “L” = 256Fs “H” = 128Fs (Connecting to ground)
98	PLDIVB	O	PLL output frequency select “L” = 768Fs “H” = 1024Fs (Connecting to ground)
99	CLKI	I	Master clock input
100	CLKO	O	Master clock output (Not used)
101	VSS1	—	Ground
102	VDD0	—	+3.3V
103	AVSS	—	Ground for PLL cell
104	AVDD	—	VDD for PLL cell
105	PLLCK	I/O	PLL output/test clock input
106	XPLLEN	I	PLL cell oscillation enable “L” oscillation enable “H” oscillation stop (Connecting to ground)
107	TST	I	Test data input “L” = normal	“H” = test (Connecting to ground)
108	LRCT	I	Frequency counter input (Connecting to ground)
109	LROUT	O	LRCK0 divider output
110	BKOUT	O	BCK0 divider output
111	VSS2	—	Ground
112	VDD1	—	+3.3V
113	BCK0	I	BCK input
114	BCK1	I	BCK input
115	LRCK0	I	LRCK input
116	LRCK1	I	LRCK input
117 – 120	SIA – SID	I	Serial data input

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