Sun Microsystems X4600 M2 manual Memory Interface, Chip-to-Chip Interconnect

Sun Microsystems, Inc.

to 8 GB/sec. aggregate bandwidth per link, enabling a peak bandwidth of 24 GB/sec. per processor. The AMD Opteron processor with HyperTransport Technology provides a scalable direct connection between processors, I/O subsystems, and other chipsets. HyperTransport technology helps reduce the number of buses in a system, which can reduce system bottlenecks and enable today's faster microprocessors to use system memory more efficiently in high-end multiprocessor systems.

Memory Interface

In traditional x86 Northbridge/Southbridge architectures, processors share a memory controller and are not directly connected to one another. Memory transactions must propogate through the Northbridge chip fabric. This presents a bottleneck at the front-side bus that greatly reduces productivity and performance potential. In a Direct Connect Architecture, each CPU has its own integrated memory controller, which allows for more linear, symmetrical multiprocessing and optimized memory performance. This direct connection to the memory controller significantly reduces the memory latency seen by the processor. Latency will continue to drop as the processor frequency scales.

Additionally, hardware and software memory pre-fetching mechanisms can further reduce the effective memory latency seen by the processor. This reduction in memory latency, coupled with the additional increase in memory bandwidth available directly to the processor (resulting from this platform architecture design optimization), is critical, as it greatly enhances system performance across all application segments.

Chip-to-Chip Interconnect

Current interface schemes offer throughput performance from 266 MB/sec. to 1 GB/sec. Although desktop platforms may find these rates sufficient, workstation, server, and other future platforms require a more robust interface. The simultaneous integration of high-speed technologies (such as Gigabit Ethernet, PCI-X, and the InfiniBand Architecture) onto high-end platforms will quickly dwarf the bandwidth capabilities of existing interfaces. Direct Connect Architecture using HyperTransport Technology provides a high-speed, chip- to-chip interconnect that virtually eliminates the I/O performance bottleneck while providing ample performance headroom for future growth.

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