Sun Microsystems, Inc.
In Sun Fire X4600 M2 systems, each processor contains an integrated memory controller that supports a 128-
bit-wide path to memory and three 16x16-bit HyperTransport links. Each HyperTransport link runs at speeds up
to 1 GHz and is clocked on both edges of the clock pulse, which allows for a maximum of 4 GB/sec. (2
gigatransfers/sec., 2 bytes wide) throughput in each direction (8 GB/sec. aggregate data rate bi-directionally).
Memory support is for registered DDR2/667 240-pin SDRAM DIMMs. There are four or eight DIMM slots per
CPU. DIMMS are accessed in pairs with an available memory bandwidth up to 10.7 GB/sec. (with PC6300) per
processor.
Memory capacity scales with the number of processors, so memory attached to an unpopulated processor
socket is unaddressable. As a result, a single processor machine can support a maximum of four DIMMs, while
a fully-populated, eight-CPU server can support a maximum of 32 or 64 DIMMS (X4600 or X4600 M2) with up
to 256 GB (64 x 4GB) of memory.
The AMD processor does support up to eight DIMMs per CPU. However, using more than four DIMMs requires
clocking down DIMM speed to 533 MHz, even if the DIMMs used are of the highest speed bin.
AMD Opteron Processor
Features of the AMD Opteron processor in the Sun Fire X4600 and Sun Fire X4600 M2 servers include:
•Up to eight Single-Core or Dual-Core AMD Opteron 800 Series processors (Sun Fire X4600).
•Up to eight Dual-Core AMD Opteron 8000 Series processors (Sun Fire X4600 M2).
•x64 architecture (64-bit extensions) with AMD Direct Connect Architecture using HyperTransport
Technology.
•PowerNow! support to dynamically adjust performance based on CPU utilization (voltage and frequency are
adjusted depending on kernal load). By default, PowerNow! is disabled in BIOS.
•Native support for 32-bit x86 ISA, SSE, SSE2, MMX, and 3DNow!
•Three HyperTransport links supporting up to 8 GB/sec. of direct inter-processor and I/O bandwidth per link.
•ECC protection for L1 data cache, L2 unified cache, and DRAM with hardware scrubbing of all ECC
protected arrays.
•CPU L1 Instruction cache: 64 KB two-way associative, parity protected with advanced branch prediction.
•CPU L1 Data cache: 64 KB two-way associative, ECC protected.
•Two 64-bit operations per cycle, three-cycle latency.
•CPU L2 cache: 1 MB 16-way associative, ECC protected.
•Exclusive cache architecture storage, in addition to L1 caches.
•256 TB of memory address space.
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