Theory of Operation
Theory of Operation
3Ć8

Trigger Logic A1Ă 3 Ċ Triggerlogic is the digital part of the trigger

system. It is composed of discrete positive referenced ECL logic. Trigger
logic performs the following functions.
HIt selects the trigger event. The CPU serially selects analog trigger
(TRIG_GATE), field 1,field 2 (TV_FIELDS), any field (ANY_FIELD), or
lines (CSYNC). The different modes are dependent on trigger related
frontĆpanel settings.
HIt accepts all trigger events and decides which event will finish the
acquisition. The analog holdoff qualifies the main trigger event to
become the main used trigger.
CPU System A1Ă 6
The CPU system contains a 68331 microprocessor that controls the entire
instrument. The processor passes waveforms and text on to the display
system. The Main Board contains both the CPU and display systems, and
the firmware ROMs.
The CPU coordinates all oscilloscope activities. It also directs the activities of
the frontĆpanel processor using a serial interface.
CPU Clocks Ċ Processor clocks are derived from 60.6MHz oscillator
Y701. The TBC divides the 60.6 MHz clock by 4 for a PROC_CLK of
15.15ĂMHz.
Interrupts Ċ The 68331 supports seven levels ofautoĆvectored interrupts
dedicated to different interrupt levels. The TBC, display system, and option
board generate interrupts.
Reset Ċ The CPU resets both at powerĆonand powerĆoff using the reset
signal. Reset controller U606 controls system reset. PowerĆonreset asserts
for a minimum of 400 ms after the +5 V supply stabilizes. PowerĆoffreset
asserts when the supply falls below a usable threshold.
Memory Ċ The memory subsystem includes 32 K 8NVRAM for
powerĆoff storage and dynamic RAM for the main system RAM.
The NVRAM (U605) consists of a single nonvolatile memory IC. This RAM
provides longĆterm powerĆoff storage of frontĆpanel settings, waveforms, and
calibration constants.
Dynamic RAM (U704 for models TDS 310, TDS 350 and TDS 320 with
SN B030100 and above; U702-U705 for model TDS 320 with SN B029999
and below) is organized as 256 K 16 for a total of 512 kbytes. It is
controlled by the ADG250 display controller (U701).
During a normal 68331 access the ADG250 multiplexes the address (on A2
to A19) onto the A0 to A8 address lines and creates control signals ~RAS,
~CAS,~XWL,~XWU, and ~XOE.