
Appendix A: Options and Accessories
Clock Output. The same clock that is fed to the AWG2021 internal D/A converter is buffered like the data and delivered to the output connector. The clock output is differential ECL output.
Figure
|
|
| 12 Bit |
Wveform | Dt | 12 |
|
| D/A | ||
Memory |
|
| |
|
|
| |
|
|
|
|
Clock
Buffer
12 |
| 12 |
|
|
|
| Dt | 24 | ||
|
|
|
|
| ||||||
|
|
|
|
| ||||||
|
|
|
|
| ||||||
Ltch |
|
|
|
| ||||||
|
|
|
| |||||||
|
|
|
| |||||||
|
|
|
| |||||||
|
|
|
| |||||||
|
|
|
| |||||||
|
|
|
| |||||||
|
|
|
| |||||||
|
|
|
| |||||||
|
|
|
| |||||||
|
|
|
|
|
| D0 - D11 |
| |||
|
|
|
|
|
|
|
| |||
|
|
|
|
|
|
|
| |||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| D0 - D11 |
| ||
|
|
|
|
|
|
|
| |||
|
|
|
|
|
|
|
| |||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Clock 2
Clock
Clock
Output
Connector
Option 03
Figure A1: Block Diagram
A2 | AWG2021 User Manual |