Setting Functions
JP001 setting table: DIR1703 system clock and crystal frequency
fS in X’tal |
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Mode | 128 fS | 256 fS | 384 fS | 512 fS | BRSEL Jumper Position |
32 kHz | 4.096 MHz | 8.192 MHz | 12.288 MHz | 16.384 MHz | BFRAME |
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44.1 kHz | 5.6448 MHz | 11.2896 MHz | 16.9344 MHz | 22.5792 MHz | EMFLG |
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48 kHz | 6.144 MHz | 12.288 MHz | 18.432 MHz | 24.576 MHz | OPEN (no jumper) |
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88.2 kHz | 11.2896 MHz | 22.5792 MHz | 33.8688 MHz | 45.1584 MHz | URBIT |
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96 kHz | 12.288 MHz | 24.576 MHz | 36.864 MHz | 49.152 MHz | CSBIT |
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Sample of a of JP001 setting
Target: system clock: 256 fS and fS = 48 kHz in the X’tal mode
In the preceding table, the frequency listed where the
The cutoff frequency of the LPF inserted in the DAC output is chosen by these jumpers. The initial setting (all pins shorted) is 54 kHz at the time of shipment. The cutoff frequency with all
There are two pairs of ADC input connectors. One pair is coupled to the PCM3010 through capacitors (C121, C122). The other pair is connected through a
The input connectors are chosen by JP105 and JP106. When the jumpers are on
When the jumpers are on
ADC | Connector No. | Details |
CN101 | ||
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CN102 | ||
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CN103 | ||
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CN104 |
JP107: Connection of PCM3010 and S/PDIF I/O circuits
This is the header pin which connects the clock input and data I/O of the PCM3010 with an S/PDIF I/O circuit. All pin positions have shorting plugs installed at the time of shipment.
For evaluating the PCM3010 with other DSPs, DIRs, and DITs, JP107 jumpers are removed. Connection to the alternative devices is made through the row of JP107 pins that is wired to the PCM3010.