Texas Instruments SLVU013 1.4 Design Specification Summary

Design Specification Summary

1-5

Introduction

1.4 Design Specification Summary

This section summarizes the design requirements of the EVM converters.

Although every attempt was made to accurately describe the performance of

the EVM converters and the TPS56xx controllers, in case of conflicts, the

TPS56xx data sheet takes precedence over this document.

The TPS56xx family of controllers provides the necessary regulation

functions. In addition to a reference voltage accuracy of ±1% over the full

operating temperature range, the controller has remote sense inputs to

provide a precisely regulated output voltage. The controller also provides

undervoltage lock-out, overload protection, overvoltage protection, and

overtemperature protection. The controller has a logic level INHIBIT input to

control the converter turn-on and turn-off and a power good output to indicate

output voltage status. Undervoltage lock-out prevents operation of the power

supply when the 12 Vdc input voltage is not sufficient for proper operation.

Overload protection protects the power supply from accidental overloads or

short circuits. Overvoltage protection prevents damage to the load in the event

of an internal power supply failure or presence of high voltages on the output

from an external condition. Both overvoltage and overcurrent cause a latched

shutdown. Both power MOSFETs are driven to an OFF state. Recovery from

shutdown requires removal of the 12 V control input supply for reset. Table 1–2

lists the operating specifications of the EVM converters.

Table 1–2.EVM Converter Operating Specifications

Specification Min Typ Max Units

Power input voltage range 4.5 6 V

Control input voltage range 10.8 13.2 V

Static voltage tolerance†

SLVP111 (3.3 V)

SLVP112 (2.5 V)

SLVP113 (1.8 V)

SLVP114 (1.5 V)

3.27

2.47

1.78

1.48

3.30

2.50

1.80

1.50

3.33

2.53

1.82

1.52

V

V

V

Line regulation‡± 0.05% ± 0.1%

Load regulation§± 0.2% ± 0.4%

Transient response¶± 100

50 mV pk

µsec

Output current range#06A

Current limit#10 A

Operatin

g

fre

q

uenc

yk

O erating

frequency

SLVP111 (3.3 V) 135 kHz

()

SLVP112 (2.5 V) 225 kHz

SLVP113 (1.8 V)

SLVP114(1 8 V)

295

360

kHz

kH

S

LVP114

(

1.8 V

)

360 kHz

Contents

Main Page Preface Read This First About This Manual How to Use This Manual Information About Cautions and Warnings Related Documentation From Texas Instruments Synchronous Buck Converter Design Using TPS56xx Controllers in SLVP10x EVMs Users Guide The TPS56xx Family of Power Supply Controllers FCC Warning Trademarks Contents Figures Tables Page Chapter 1 Introduction Topic Page 1.1 Synchronous Buck Regulator Operation Figure 11. Simplified Synchronous Buck Converter Schematic 1.2 Hysteretic Control Operation Figure 12. Simplified Hysteretic Controlled Output Voltage Waveform 1.3 Design Strategy Providing a DSP Power Solution from 5 V or 3.3 V Only Systems Table 11.Summary of EVM Converter Modules 1.4 Design Specification Summary Table 12.EVM Converter Operating Specifications Design Specification Summary Table 12.EVM Converter Operating Specifications (Continued) Schematic Introduction 1-7 1.5 Schematic Figure 13. SLVP111114 EVM Converter Schematic Diagram Bill of Materials 1.6 Bill of Materials Table 13 lists materials required for the SLVP111114 EVMs. Table 13.SLVP111114 EVMs Bill of Materials Bill of Materials Introduction Table 13.SLVP111114 EVMs Bill of Materials (Continued) 1.7 Board Layout Page Page Chapter 2 Design Procedure hysteretic Topic Page 2.1 TPS56xx Functions TPS56xx Functions Design Procedure 2-3 Figure 21. TPS56xx Functional Block Diagram 2.1.1 VCC Undervoltage Lockout 2.1.2 Inhibit 2.1.3 Slowstart Design 2.1.4 Hysteresis Setting Page 2.1.5 Noise Suppression Figure 22. Block Diagram Showing Noise Suppression Circuits 2.1.6 Overcurrent Protection Figure 23. V DS Sensing Circuit Page 2.1.7 Overvoltage Protection 2.1.8 Power Good 2.1.9 Bias 2.1.10 Gate Drivers TPS56xx Functions Figure 24. Gate Driver Block Diagram Figure 25. IV Characteristic Curve for Low-Side Gate Drivers 2.1.10.1 Low-Side Driver Controls 2.1.10.2 High-Side Driver 2.1.10.3 Grounding Layout Guidelines . 2.2.3.1 Output Capacitance ESR mV m 2.2.3.2 Output Inductance 2.2.4 Switching Frequency Analysis External Component Selection 2-18 Figure 26. Output Ripple Voltage Detail L Io DS(on) ) Page 2.2.5 Power MOSFET Selection Test Results 3.1 Test Summary 3.1.1 Static Line and Load Regulation 3.1.2 Output Voltage Ripple 3.1.3 Efficiency and Power Losses 3.1.4 Output Start-Up and Overshoot 3.1.5 Frequency Variation Designing Fast Response Synchronous Buck Converters Using the TPS5210 controller A Fast, Efficient Synchronous-Buck Controller for Microprocessor Power Supplies 3.1.6 Load Current Transient Response 3.1.8 Conclusion 3.2 Test Setup R Watts R + 3-7 3.3 Test Results Figures 32 to 3102 show test results for the SLVP111. Figure 32. SLVP111 Measured Load Regulation SLVP111 MEASURED LOAD REGULATION Figure 33. SLVP111Measured Efficiency Figure 34. SLVP111Measured Power Dissipation SLVP111 MEASURED POWER DISSIPATION Figure 35. SLVP111Measured Switching Frequency SLVP111 MEASURED SWITCHING FREQUENCY 3-9 Figure 36. SLVP111 Measured Switching Waveforms Figure 37. SLVP111Measured Start-Up (INHIBIT) Waveforms 3-10 Figure 38. SLVP111 Measured Start-Up (V Figure 39. SLVP111Measured Start-Up (V 3-11 Figure 310. SLVP111 Measured Load Transient Waveforms Figure 311. SLVP112 Measured Load Regulation SLVP112 MEASURED LOAD REGULATION 3-12 Figure 312. SLVP112 Measured Efficiency SLVP111 MEASURED EFFICIENCY Figure 313. SLVP112 Measured Power Dissipation SLVP111 MEASURED POWER DISSIPATION 3-13 Figure 314. SLVP112 Measured Switching Frequency SLVP112 MEASURED SWITCHING FREQUENCY Figure 315. SLVP112 Measured Switching Waveforms 3-14 Figure 316. SLVP112 Measured Start-Up (INHIBIT) Waveforms Figure 317. SLVP112 Measured Start-Up (V 3-15 Figure 318. SLVP112 Measured Start-Up (V Figure 319. SLVP112 Measured Load Transient Waveforms 3-16 Figure 320. SLVP113 Measured Load Regulation SLVP113 MEASURED LOAD REGULATION Figure 321. SLVP113 Measured Efficiency SLVP113 MEASURED EFFICIENCY 3-17 Figure 322. SLVP113 Measured Power Dissipation SLVP113 MEASURED POWER DISSIPATION Figure 323. SLVP113 Measured Switching Frequency SLVP113 MEASURED SWITCHING FREQUENCY 3-18 Figure 324. SLVP113 Measured Switching Waveforms Figure 325. SLVP113 Measured Start-Up (INHIBIT) Waveforms 3-19 Figure 326. SLVP113 Measured Start-Up (V Figure 327. SLVP113 Measured Start-Up (V 3-20 Figure 328. SLVP113 Measured Load Transient Waveforms Figure 329. SLVP114 Measured Load Regulation SLVP114 MEASURED LOAD REGULATION 3-21 Figure 330. SLVP114 Measured Efficiency SLVP114 MEASURED EFFICIENCY Figure 331. SLVP114 Measured Power Dissipation SLVP114 MEASURED POWER DISSIPATION 3-22 Figure 332. SLVP114 Measured Switching Frequency SLVP114 MEASURED SWITCHING FREQUENCY Figure 333. SLVP114 Measured Switching Waveforms 3-23 Figure 334. SLVP114 Measured Start-Up (INHIBIT) Waveforms Figure 335. SLVP114 Measured Start-Up (V 3-24 Figure 336. SLVP114 Measured Start-Up (V Figure 337. SLVP114 Measured Load Transient Waveforms