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Texas Instruments SLVU013 Figure 22. Block Diagram Showing Noise Suppression Circuits

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TPS56xx Functions

2-7

Design Procedure

2.1.5 Noise Suppression

Hysteretic regulators, by nature, have a fast response time to VO transients

and are thus inherently noise sensitive due to the very high bandwidth of the

controller. Noise suppression circuits were added to the TPS56xx to improve

the noise immunity, as shown in Figure 2–2. Internal low-pass filters with a pole

frequency of 5 MHz were added to the inputs of the hysteretic comparator.

These low-pass filters are referenced to the same analog ground as the

hysteretic comparator. There is a common-mode filter with a 4-MHz pole

between VREFB and VHYST to filter out noise between these pins. A double

pulse suppression circuit prohibits spurious pulses from propagating to the

gate drivers. The double pulse suppression circuit becomes active when the

comparator has toggled or when the LOHIB pin (which is connected to the

power MOSFETs) has transitioned, providing additional noise immunity from

internally and externally generated noise. The suppression circuit is active for

150 ns.

A low-pass filter is recommended between VO and the VSENSE pin (R1 and

C3 in Figure 2–2); recommended values are 100 ohms and 1 nF. This low-pass

filter is included in the evaluation design of Figure 1–3 (R8, R11, and C20).

Figure 2–2. Block Diagram Showing Noise Suppression Circuits

Adaptive

Deadtime

Control

HIGHDR C1

L1

Vin

L2

C2

LOHIB

LOWDR

Vphase

VO

TPS56xx Synchronous-Buck Controller

C3R2

Hysteresis

Setting

VSENSE R1

VHYST

+–

VREFB

R3

R4

R5

R6

Reference Vref

IOUT

VH_SET

Double Pulse

Suppression

Circuit

5 MHz

Filter

5 MHz

Filter

4 MHz

Filter

Vds

Sensing

2.1.6 Overcurrent Protection

Overcurrent protection is provided by measuring the on-state voltage of the

high-side MOSFET, conditioning the measured voltage, and comparing the

result to a reference voltage. If the output current exceeds the current limit

setpoint, a fault latch is set and the output drivers are turned off. Vcc (12 V)

must be reduced to below the undervoltage lockout value to restart the

converter.

A sample-and-hold circuit measures the power supply output current by

sensing the on-state drain-to-source voltage of the high-side MOSFET (Q1 in

Contents

Main Page Preface Read This First About This Manual How to Use This Manual Information About Cautions and Warnings Related Documentation From Texas Instruments Synchronous Buck Converter Design Using TPS56xx Controllers in SLVP10x EVMs Users Guide The TPS56xx Family of Power Supply Controllers FCC Warning Trademarks Contents Figures Tables Page Chapter 1 Introduction Topic Page 1.1 Synchronous Buck Regulator Operation Figure 11. Simplified Synchronous Buck Converter Schematic 1.2 Hysteretic Control Operation Figure 12. Simplified Hysteretic Controlled Output Voltage Waveform 1.3 Design Strategy Providing a DSP Power Solution from 5 V or 3.3 V Only Systems Table 11.Summary of EVM Converter Modules 1.4 Design Specification Summary Table 12.EVM Converter Operating Specifications Design Specification Summary Table 12.EVM Converter Operating Specifications (Continued) Schematic Introduction 1-7 1.5 Schematic Figure 13. SLVP111114 EVM Converter Schematic Diagram Bill of Materials 1.6 Bill of Materials Table 13 lists materials required for the SLVP111114 EVMs. Table 13.SLVP111114 EVMs Bill of Materials Bill of Materials Introduction Table 13.SLVP111114 EVMs Bill of Materials (Continued) 1.7 Board Layout Page Page Chapter 2 Design Procedure hysteretic Topic Page 2.1 TPS56xx Functions TPS56xx Functions Design Procedure 2-3 Figure 21. TPS56xx Functional Block Diagram 2.1.1 VCC Undervoltage Lockout 2.1.2 Inhibit 2.1.3 Slowstart Design 2.1.4 Hysteresis Setting Page 2.1.5 Noise Suppression Figure 22. Block Diagram Showing Noise Suppression Circuits 2.1.6 Overcurrent Protection Figure 23. V DS Sensing Circuit Page 2.1.7 Overvoltage Protection 2.1.8 Power Good 2.1.9 Bias 2.1.10 Gate Drivers TPS56xx Functions Figure 24. Gate Driver Block Diagram Figure 25. IV Characteristic Curve for Low-Side Gate Drivers 2.1.10.1 Low-Side Driver Controls 2.1.10.2 High-Side Driver 2.1.10.3 Grounding Layout Guidelines . 2.2.3.1 Output Capacitance ESR mV m 2.2.3.2 Output Inductance 2.2.4 Switching Frequency Analysis External Component Selection 2-18 Figure 26. Output Ripple Voltage Detail L Io DS(on) ) Page 2.2.5 Power MOSFET Selection Test Results 3.1 Test Summary 3.1.1 Static Line and Load Regulation 3.1.2 Output Voltage Ripple 3.1.3 Efficiency and Power Losses 3.1.4 Output Start-Up and Overshoot 3.1.5 Frequency Variation Designing Fast Response Synchronous Buck Converters Using the TPS5210 controller A Fast, Efficient Synchronous-Buck Controller for Microprocessor Power Supplies 3.1.6 Load Current Transient Response 3.1.8 Conclusion 3.2 Test Setup R Watts R + 3-7 3.3 Test Results Figures 32 to 3102 show test results for the SLVP111. Figure 32. SLVP111 Measured Load Regulation SLVP111 MEASURED LOAD REGULATION Figure 33. SLVP111Measured Efficiency Figure 34. SLVP111Measured Power Dissipation SLVP111 MEASURED POWER DISSIPATION Figure 35. SLVP111Measured Switching Frequency SLVP111 MEASURED SWITCHING FREQUENCY 3-9 Figure 36. SLVP111 Measured Switching Waveforms Figure 37. SLVP111Measured Start-Up (INHIBIT) Waveforms 3-10 Figure 38. SLVP111 Measured Start-Up (V Figure 39. SLVP111Measured Start-Up (V 3-11 Figure 310. SLVP111 Measured Load Transient Waveforms Figure 311. SLVP112 Measured Load Regulation SLVP112 MEASURED LOAD REGULATION 3-12 Figure 312. SLVP112 Measured Efficiency SLVP111 MEASURED EFFICIENCY Figure 313. SLVP112 Measured Power Dissipation SLVP111 MEASURED POWER DISSIPATION 3-13 Figure 314. SLVP112 Measured Switching Frequency SLVP112 MEASURED SWITCHING FREQUENCY Figure 315. SLVP112 Measured Switching Waveforms 3-14 Figure 316. SLVP112 Measured Start-Up (INHIBIT) Waveforms Figure 317. SLVP112 Measured Start-Up (V 3-15 Figure 318. SLVP112 Measured Start-Up (V Figure 319. SLVP112 Measured Load Transient Waveforms 3-16 Figure 320. SLVP113 Measured Load Regulation SLVP113 MEASURED LOAD REGULATION Figure 321. SLVP113 Measured Efficiency SLVP113 MEASURED EFFICIENCY 3-17 Figure 322. SLVP113 Measured Power Dissipation SLVP113 MEASURED POWER DISSIPATION Figure 323. SLVP113 Measured Switching Frequency SLVP113 MEASURED SWITCHING FREQUENCY 3-18 Figure 324. SLVP113 Measured Switching Waveforms Figure 325. SLVP113 Measured Start-Up (INHIBIT) Waveforms 3-19 Figure 326. SLVP113 Measured Start-Up (V Figure 327. SLVP113 Measured Start-Up (V 3-20 Figure 328. SLVP113 Measured Load Transient Waveforms Figure 329. SLVP114 Measured Load Regulation SLVP114 MEASURED LOAD REGULATION 3-21 Figure 330. SLVP114 Measured Efficiency SLVP114 MEASURED EFFICIENCY Figure 331. SLVP114 Measured Power Dissipation SLVP114 MEASURED POWER DISSIPATION 3-22 Figure 332. SLVP114 Measured Switching Frequency SLVP114 MEASURED SWITCHING FREQUENCY Figure 333. SLVP114 Measured Switching Waveforms 3-23 Figure 334. SLVP114 Measured Start-Up (INHIBIT) Waveforms Figure 335. SLVP114 Measured Start-Up (V 3-24 Figure 336. SLVP114 Measured Start-Up (V Figure 337. SLVP114 Measured Load Transient Waveforms