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Digital Audio Interface (J60)
2.6Digital Audio Interface (J60)
The digital audio interface contains digital audio signal data (I2S), clocks, etc. Please see the TAS5508B Data Manual for signal timing and details not explained in this document.
Table 2-8. J60 Pin Description
PIN NO. | DESCRIPTION | |
1 | GND | Ground |
2 | MCLK | Master clock input. Low jitter system |
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| clock for PWM generation and |
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| reclocking. Ground connection from |
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| source to TAS5508B must be a low |
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| impedance connection. |
3 | GND | Ground |
4 | SDIN1 | I2S data 1, channel 1 and 2 |
5 | SDIN2 | I2S data 2, channel 3 and 4 |
6 | SDIN3 | I2S data 3 |
7 | SDIN4 | I2S data 4 |
8 | — | Reserved |
9 | — | Reserved |
10 | GND | Ground |
11 | SCLK | I2S bit clock |
12 | GND | Ground |
13 | LRCLK | I2S |
14 | GND | Ground |
15 | — | Reserved |
16 | GND | Ground |
SLEU071 | System Interfaces | 13 |
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