Texas Instruments TPS40051 manual Short Circuit Protection, Snubber Component Selection

SLUU161 – April, 2003

4.8Short Circuit Protection

The TPS40051 implements short circuit protection by comparing the voltage across the topside MOSFET while it is ON to a voltage developed across RLIM due to an internal current source of 10 µ A inside pin 16. Both of these voltages are negative with respect to VIN. From the datasheet equation, RLIM is defined as:

RLIM	+ R9 +	IOC RDS(on) (max)	+	VOS	+ (W)	(10)
		1.12 ISINK		ISINK

where

•

•

IOC is the overcurrent set point equal to the DC output current plus one-half the inductor ripple current

VOS is the overcurrent comparator offset, and Isink is the current into ILIM (pin 16).

Using worst case tolerances the value of RLIM should be maximized to ensure that the converter can deliver full rated current under all conditions. In a worst case condition, RLIM=R9 and

R	LIM	+		(15 A ) 1.5 A)	(7.9 mW	1.45)	)	* 30 mV	+ 16.0 kW	(11)
			1.12		8.65 mA
								8.65 mA

The standard value of 16.2 kΩ was selected. This ensures that we can deliver a minimum of 15 A before current limit is activated. There is also a small capacitor, C7, placed in parallel with R9 to filter the signal.

4.9Snubber Component Selection

Initially, the junction of Q1, Q2, and L1 was ringing at a frequency near 100 MHz with a peak voltage near 30 V. This was due to the extremely fast switching speed of the MOSFETs and the lack of any cross–conduction. C13 was added to shunt the high-frequency ringing to ground and the peak voltage is now below 25 V.

4.10 Compensation Components

The TPS40051 uses voltage mode control with feed-forward in conjunction with a high-frequency error amplifier to implement closed loop control. The power circuit L-C double pole corner frequency fC occurs at 3.8 kHz, and the output capacitor ESR zero is located at approximately 38 kHz. The feedback compensation network is implemented to provide two zeroes and three poles. The first pole is placed at the origin to improve DC regulation.

The first zero is placed at 2.8 kHz, just below the L-C corner frequency.

fZ1 +	1
	2p R5 C5

The second zero is selected to be coincident with the L-C corner frequency of 3.8 kHz,

fZ2	+		1
		2p	(R7 ) R8) C6

The second pole is placed near the ESR zero frequency at 37 kHz.

fP1 + 2p R5 1 ￿C4 C5￿ C4)C5

and the third pole is placed at 150 kHz, which is one-half the switching frequency.

fP2 +	1
	2p R8 C6

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TPS40051-Based Design Converts 12-V Bus to 1.8 V at 15 A (SLUP195) 9