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Texas Instruments TPS40090EVM-002 manual Compensation Components, + 354 kHz, 2p R11 C11

Models: TPS40090EVM-002

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SLUU195 − June 2004

4.8Compensation Components

The TPS40090 uses peak current mode control. Type II network is used here, which is implemented to provide one zero and two poles. The first pole is placed at the origin to improve DC regulation.

The ESR zero of the power stage is:

fESRZ	+		1	+ 354 kHz
		2p	RC COUT

The zero is placed near 3.96 kHz to produce a reasonable time constant.

fZ +	1
	2p R11 C11

The second pole is placed at ESR zero (354 kHz).

fP1 +	1
fP1 +	2p R11	C11 C12
		C11 C12
		C11)C12

The resulting values selected for this design are:

•R11 = 40.2 kΩ

•C11 = 1000 pF

•C12 = 10 pF

(12)

(13)

(14)

TPS40090 Multi-Phase Buck Converter and TPS2834 Drivers Steps-Down from 12-V to 1.5-V at 100 A

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Texas Instruments TPS40090EVM-002 manual Compensation Components, + 354 kHz, 2p R11 C11

Contents

User’s Guide Using the TPS40090EVM-002User’s Guide EVM IMPORTANT NOTICE DYNAMIC WARNINGS AND RESTRICTIONS Contents 1 Introduction 2 Features 3 Schematic 4 Component Selection Systems Power5 Test Setup 6 Test Results/Performance Data 7 Layout Considerations 8 EVM Assembly Drawing and PCB Layout 9 List of MaterialsSchematic FeaturesTable 1. TPS40090EVM−002 Performance Summary SLUU195 − JuneTRANSEN SLUU195 − June4.1 Frequency of Operation 4 Component Selection4.3 Input Capacitor Selection 4.2 Inductance ValueIOUT k N PH, D + if N PH v 1, DI OUTD, DI OUT N PH, D 4.4 Output Ripple Cancellation and Capacitor SelectionK N PH, D + Figure 5. Output Ripple Current Cancellation4.6 Current Sensing 4.5 MOSFET Selection0.6mH 4.7 Overcurrent Limit Protection + 354 kHz 4.8 Compensation Components2p R11 C11 Figure 7. Connections for the Test 5 Test Setup6 Test Results and Performance Data 6.1 Efficiency and Power Loss6.3 Output Ripple and Noise 6.2 Closed-Loop PerformanceFigure 10. Bode Plot Figure 11. Output NoiseFigure 12. Transient Response 6.4 Transient ResponseFigure 13. J11 Short Circuit 6.5 Start up with Pre-Biased OutputFigure 14. J11 Open Circuit 7 Layout Considerations Figure 15. Top Side Component Assembly Figure 16. Bottom Assembly 8 EVM Assembly Drawing and PCB LayoutSLUU195 − June SLUU195 − June Figure 17. Top Side Copper Figure 18. Internal 1 Ground PlaneSLUU195 − June Figure 19. Internal 2 Power Plane Figure 20. InternalSLUU195 − June Figure 21. Internal Figure 22. Bottom Layer CopperTable 2. List of Materials 9 List of MaterialsSLUU195 − June Reference SLUU195 − JuneDescription SizeProducts IMPORTANT NOTICEApplications