6.2.4.Timing of Host Interface (Ultra DMA )
Figure 12 shows the Host Interface Ultra DMA word Timings
DMARQ | tUI |
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DMACK- |
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| tACK | tFS | t2CYC |
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STOP |
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| tCYC | tCYC | |
| tENV |
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DMARDY |
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| t2AD |
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| t2IORDY |
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STROBE |
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| tDVS tDVH tDVS | tDVH | tDVS tDVH | |
DD |
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(15:0) |
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tMLI |
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tRP |
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tLI | tACK |
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tRFS |
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tDVS | tDVH |
CRC | |
| Ultra DMA Mode 2 | Min time (ns) | Max time | (ns) |
| timing parameters min (ns) max (ns) | |||
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t2CYC | Typical Sustained Average Cycle time | 120 |
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tCYC | Cycle time | 55 |
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tDVS | Data Setup time | 34 |
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tDVH | Data Hold time | 6 |
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tUI | Unlimited Interlock time | 0 |
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tACK | Setup and Hold Time for DMACK- | 20 |
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tENV | Envelope time | 20 | 70 |
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t2AD | Minimum Delay time for Driver | 0 |
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t2IORODY | Minimum time for DMACK- | 20 |
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tFS | First STROBE time | 0 | 170 |
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tRFS |
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tRP | 100 |
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tLI | Limited Iuterlock time | 0 | 150 |
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tMLI | Interlock with minimum | 20 |
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Figure 12 Host Interface Timing (Ultra DMA)
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