Toshiba XM-7002B 17/27

17/27 XM-7002B Rev.1.0

6.2.4.Timing of Host Interface (Ultra DMA )

Figure 12 shows the Host Interface Ultra DMA word Timings

DMARQ

DMACK-

STOP

DMARDY

STROBE

(15:0)

tMLI

tUI

tACK tFS

tENV

t2AD

t2IORDY

t2CYC tRP

tRFS

tLI tACK

tDVS tDVH

CRC

tDVHtDVS

tDVH

tDVS

tDVHtDVS

tCYC tCYC

Ultra DMA Mode 2

timing parameters min (ns) max (ns) Min time (ns) Max time (ns)

t2CYC Typical Sustained Average Cycle time 120

tCYC Cycle time 55

tDVS Data Setup time 34

tDVH Data Hold time 6

tUI Unlimited Interlock time 0

tACK Setup and Hold Time for DMACK- 20

tENV Envelope time 20 70

t2AD Minimum Delay time for Driver 0

t2IORODY Minimum time for DMACK- 20

tFS First STROBE time 0170

tRFS Ready-to-Final STROBE time 50

tRP Ready-to-Pause time 100

tLI Limited Iuterlock time 0 150

tMLI Interlock with minimum 20

Figure 12 Host Interface Timing (Ultra DMA)

Contents

Main TOSHIBA Notice Contents Page 1/27 2/27 3/27 4/27 Page Page Page 8/27 Page 10/27 11/27 XM-7002B BLOCK DIAGRAM Figure 5 Basic configuration of XM-7002B + 5 V 12/27 13/27 14/27 6.2.1.Signal Specifications Figure 9 shows the Signal Specifications Figure 9 Signal Specifications 15/27 16/27 6.2.3.Timing of Host Interface (DMA Multi) Figure 11 shows the Host Interface DMA multi word Timings Figure 11 Host Interface Timing (DMA Multi) *1: In all timing diagrams, the low line indicator negated, and the upper line indicators asserted. 17/27 Figure 12 Host Interface Timing (Ultra DMA) 18/27 Figure 13 Connector pin assignments 19/27 20/27 21/27 7. Power Requirements 22/27 23/27 24/27 25/27 26/27 TOSHIBA EU-Declaration of Conformity Annex 1 27/27 EU-Declaration of Conformity CD-ROM Drive XM-7002B X Manufactuer(s) Location Address