Toshiba XM-7002B 16/27

16/27 XM-7002B Rev.1.0

6.2.3.Timing of Host Interface (DMA Multi)

Figure 11 shows the Host Interface DMA multi word Timings

DMARQ

DMACK-*1

DIOR/DIOW-*1

Read

DD0-1

Write

DD0-1

tI tJ

*1: In all timing diagrams, the low line indicator negated, and the upper line

indicators asserted.

Multi word DMA Mode 2

timing parameters min (ns) max (ns) Min time (ns) Max time (ns)

t0 Cycle time 120

tC DMACK to DMREQ delay ---

tD DIOR-/DIOW- 16-bit 70

tE DIOR- data access 50

tF DIOR- data hold 5

tZ DMACK- to tristate 25

tG DIOR/DIOW- data setup 20

tH DIOW- data hold 10

tI DMACK to DIOR-/DIOW- setup 0

tJ DIOR-/DIOW- to DMACK hold 5

tKr DIOR- negated pulse width 25

tKw DIOW- negated pulse width 25

tLr DIOR- to DMREQ delay 35

tLw DIOR- to DMREQ delay 35

Figure 11 Host Interface Timing (DMA Multi)

Contents

Main TOSHIBA Notice Contents Page 1/27 2/27 3/27 4/27 Page Page Page 8/27 Page 10/27 11/27 XM-7002B BLOCK DIAGRAM Figure 5 Basic configuration of XM-7002B + 5 V 12/27 13/27 14/27 6.2.1.Signal Specifications Figure 9 shows the Signal Specifications Figure 9 Signal Specifications 15/27 16/27 6.2.3.Timing of Host Interface (DMA Multi) Figure 11 shows the Host Interface DMA multi word Timings Figure 11 Host Interface Timing (DMA Multi) *1: In all timing diagrams, the low line indicator negated, and the upper line indicators asserted. 17/27 Figure 12 Host Interface Timing (Ultra DMA) 18/27 Figure 13 Connector pin assignments 19/27 20/27 21/27 7. Power Requirements 22/27 23/27 24/27 25/27 26/27 TOSHIBA EU-Declaration of Conformity Annex 1 27/27 EU-Declaration of Conformity CD-ROM Drive XM-7002B X Manufactuer(s) Location Address