4.6Advanced Chipset Setup
This section allows you to configure the system based on the specific features of the installed chipset. This chipset manages bus speeds and the access to the system memory resources, such as DRAM and the external cache. It also coordinates the communications between the conventional ISA and PCI buses. It must be stated that these items should never be altered. The default settings have been chosen because they provide the best operating conditions for your system. You might consider and make any changes only if you discover that the data has been lost while using your system.
AMIBIOS SETUP – ADVANCED CHIPSET SETUP(C)2001 American Megatrends, Inc. All Rights Reserved
CPU Ratio Selection | Safe Mode | Available Options: | |
CPU BIST Enable | Disabled | ` Safe Mode |
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ICH Delayed Transaction | Disabled | 5.5x |
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DMA Collection Buffer Enable | Disabled | 6.0x |
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DRAM Page Closing Policy | Open | 6.5x |
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Memory Hole | Disabled | 7.0x |
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MPS Revision | 1.1 | 7.5x |
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System memory Frequency | 100MHz | 8.0x |
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SDRAM Timing by SPD | Disabled | 8.5x |
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DRAM Refresh | 15.6us | 9.0x |
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DRAM Cycle time (SCLKs) | 7/9 | 9.5x |
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CAS# Latency (SCLKs) | 3 | 10.0x |
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RAS to CAS delay (SCLKs) | 3 | 10.5x |
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SDRAM RAS# Precharge (SCLKs) | 3 | 11.0x |
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Internal Graphics Mode Select | 1MB | 11.5x |
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Display Cache Window Size | 64MB | 12.0x |
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AGP Aperture Window | 64MB |
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Local memory Frequency | 100MHz |
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Initialize Display Cache Memory | Enabled |
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Paging Mode Control | Closed |
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RAS – to CAS | Default |
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CAS Latency | Slow |
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RAS Timing | Slow |
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RAS Precharge Timing | Slow |
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CPU Latency Timer | Disabled |
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USB Function | All USB Port | ESC:Exit | :Sel |
USB Device Legacy Support | Disabled | PgUp/PgDn: Modify | |
Port 64/60 Emulation | Disabled | F1:Help | F2/F3:Color |
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