Intel 80386 Xxxxy ~j XDONTCAR~X~ x~ ~X~~lKX~ /..XXXX, Xxxxx IXXXXIXXXXI.. /..DXXXIXXX ~ Xxxxiy

intJ80386

quest, and is allowed to drive the next internally pending address onto the bus. Asserting NA # there- fore makes it impossible for the next bus cycle to again access the current address on A2-A31, such as may be required when B816 # is asserted by the external hardware.

To avoid conflict, the 80386 is designed with follow- ing two provisions:

1)To avoid conflict, the 80386 is deSigned to ignore B816# in the current bus cycle if NA# has already

been sampled asserted in the current cycle. If NA# is sampled asserted, the current data bus size is assumed to be 32 bits.

2)To also avoid conflict, if NA# and B816# are both asserted during the same sampling window, B816# asserted has priority and the 80386 acts as if NA# was negated at that time. Internal 80386 circuitry, shown conceptually in Figure 5- 18, assures that B816# is sampled asserted and NA# is sampled negated if both inputs are exter- nally asserted at the same sampling window.

CLK2[

(82384 CLK) [

A TRANSFER REQUIRING TWO

CYCLES ON 16-BIT BUS

PREVIOUS		CYCLE I~YCLE lA						CYCLE 2
CYCLE		PIPELINED			NON-PIPELINED			NON-PIPELINED
		(WRITE			WRITE)			(READ)
		PART ONE			PART TWO
T2P	TIP	T2	T2	T1	T2	T2	Tl	T2	T2P

Jl.JlilJlilJlrtIlrtIlrtIlrmrmilJlrtIl

-VV V \f\fV V V V \f

BEO#, BE1# [

BE2#, BE3#, [ A2, A31,

M/IO#,D/C#

W/R#[

ADS#[

:~

-X

-

_ /

-'---/

	ALWAYS	rx
VALID 1	/NEGATED DURING		VALID 2
	PART TWO
	VALID 1	X	VALID 2
		\
	'---V	\......../-

{C NOTE: NA# MUST BE NEGATED IN THESE T'STO ALLOW RECOGNITION OF ASSERTED BSI6# IN FINAL T2'5.

XVALID 3

I

X VALID 3

'---

/XXXX'Y ~(j '<XDON'TCAR~<X~ '<x:~ ~X~~)lK<X~ /..'X'X"X"X

32-81T BUStSIZE

	XXXXX IXXXXIXXXXI>.. /..D<XXXIXXX)(>..			~ XXXXIY '(IXXXX
							~
		16-BIT	16-BIT
		BUS SIZE	BUS SIZE
READY# [	'5<500.- -<XXIXXY ~ /..X)(IXXY			~ -<XXIXXY			~
LOCK# [		VALID 1			X	VALID 2
	dO-dIS	dO-dIS	d16-d31		- ----		dO-dl	5
DO-D1S[ .---@-{		OUT	OUT				--<m
	d16-d31	d16-d31					dl6-d31
Dt6-D31 [	. ---~-{	OUT			}-	- ---	--~
		I	I
Key: On ~ physical data pin n							231630-25

dn ~ logical data bit n

Cycles 1 and 2 are pipelined. Cycle 1a cannot be pipelined, but its address can be inferred from that of Cycle 1, to externally sirnulate address pipelining during Cycle 1a.

Figure 5·21.Using NA# and 8516#

85