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Figure 6-3. 132-Pin Ceramic PGA Package Dimensions

6.3Package Dimensions and Mounting

The initial 80386 package is a 132-pin ceramic pin grid array (PGA). Pins of this package are arranged 0.100 inch (2.54mm) center·to·center,in a 14 x 14 matrix, three rows around.

A wide variety of available sockets allow low inser- tion force or zero insertion force mountings, and a choice of terminals such as soldertail, surface mount, or wire wrap. Several applicable sockets are listed in Table 6·2.

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Image 158

Intel 80386 manual 1654189~1, Package Dimensions and Mounting

Contents

Page Inter Intel Corporation Table of Contents Chapter Architectural Compatibility Chapter Highlights Page 32-bit Architecture High-performance Implementation Highlights Extended Debugging Support Configurable ProtectionVirtual Memory Support Object Code Compatibility Summary Application Architecture Page Flags and Instruction Pointer RegistersGeneral Registers Numeric Coprocessor Registers Memory and logical Addressing Segment and Descriptor Registers Logical Address Translation Addressing Modes Data Types and Instructions Principal Data Types Stack Instructions Numeric Coprocessor Data TypesOther Instructions ~.,...I-------.-1 Byte String LII Miscellaneous Instructions Chapter System Architecture Page System Registers Multitasking Task Switching Task State Segment Addressing Address Translation Overview Segments Address Translation Overview Principal Descriptor Fields ~~~~~.II~~~ Pages Virtual Memory Linear to Physical Address Translation I I I Protection Privilege USing Privilege Levels Privileged Instructions Segment Protection Protection Interrupts and Exceptions 10. Gates as Protected Entry Points Interrupt Descriptor Table Debug Eceptions and Registers System Architecture Page Architectural Compatibility Page 80286 Compatibility Real and Virtual 86 Modes Architectural Compatibility Trapping Virtual 861\11ode System Calls Page Chapter Hardware Implementation Page Chapter Hardware Implementation Hardware Implementation Clock Data and Address Buses Bus Cycle Definition Bus Cycle Control Non-pipelined Bus Cycle Timing Bus Cycles with Pipelined Addresses Coprocessor Control Dynamic Bus SizingProcessor Status and Control Mixed 16- and 32-bit Accesses Chapter Data Sheet Page 80386 Update Notice Table of Contents Segment Descriptor Cache Descriptor Tables IntroductionInterrupt Descriptor Table Privilege Validation Functional Data Initiating and Maintaining Pipelined Address Package Thermal Specification3.4 Pipelined Address with Dynamic Data Bus Sizing Base Architecture Introduction Register Overview Instruction Pointer Register DescriptionsGeneral Purpose Registers Flags Register TSS Other Segment Physical Base Address Segment Limit Segment RegistersSegment Registers Descriptor Registers Loaded Automatically Flects the current state of the ET bit Segment Descriptor RegistersControl Registers MSW System Address Registers TS Task Switched, bitFault Linear Address Register CR2 Directory Base Register CR3 Compatibility Register AccessibilityDebug and Test Registers Gdtr Instruction Set OverviewIopl Idtr 2a Data Transfer 2 80386 Instructions2dLogical Instructions 2b Arithmetic Instructions 2g High Level Language Instructions 2e Bit Manipulation Instructions2f. Program Control Instructions 2h Protection Model 3 32-Bit Memory Addressing Modes Addressing Modes OverviewRegister and Immediate Modes Addressing Mode Calculations Differences Between 16 and 32 Bit Addresses Base Register BX,BP Index Register SI,DI Scale Factor DisplacementData Types None LilliililillIl Sign ED rrrrrrrrl Address Spaces Memory OrganizationIntroduction I/O Space Segment Register Usage Interrupt Processing InterruptsInterrupts and Ecep~ions Maskable Interrupt Non-Maskable Interrupt Software Interrupts Interrupt and Exception Priorities NMI 2.INTR Instruction Restart Reset and InitializationDouble Fault Self-Test TLB TestingTestability Debugging Support Debug Registers Breakpoint InstructionSingle-Step Trap DR3 DR1DR2 DR4 Encoding Causing Breakpoint Usage Real Mode Architecture Real Mode Introduction Debug Status Register DR6 Xchg SET/RESET/COMPLEMENTMemory Addressing ADD, OR, ADC, SBB Shutdown and Halt Reserved LocationsIntierrupts Protected Mode Addressing Addressing Mechanism Descriptor Tables Segmentation IntroductionTerminology Descriptor Tables Introduction Address DescriptorsByte Segment Base 15 Segment Limit 15 Dptm typ , data gm,nt System Descriptor Formats Word SelectorOffset 15 Offset 31 Selector Fields Differences Between 386 and 286 DescriptorsSegment Base 15 Segment Descriptor Cache Nil R~L ~~~~~~~EL~~E~ ~A~~ ~I~I! ttl ~!~~~~E L~~E~~~s~ I~I! ~ J ~~?~~~~EL~~E~B~~E ~I~I~ tJ1 Privilege Levels Protection ConceptsRules of Privilege Privilege Level Transfers RET,IRET GOT/LOTCall CALL, JMP 80386 Task Switching Call Ga~es Initialization and Transition to Protected Mode Infef Systems Tools for Building ProtectedPaging Paging Concepts Descriptor Base Register Paging OrganizationMechanism Directory Tables Level Protection R/W, U/S BitsFrame Address 31 Reserved DIRECTORY/TABLE Entries Translation Lookaside Buffer Paging Operation Virtual 8086 Environment Paging In Virtual ModeAccess Type Executing 8086 Programs Protection and 1/0 Permission Bitmap 24. Virtual 8086 Environment Memory Management Interrupt Handling Entering and Leaving Virtual Task Switches TO/FROM Virtual 8086 Mode ·25.Virtual 8086 Environment Interrupt and Call Handling For state saving i.e. push all registers in prolog, pop Introduction Clock CLK2 Data Bus do through Address Bus BEO# through BE3#, A2 through A31 Bus Cycle Definition Signals W/R#, D/C#, MIIO#, LOCK# Bus Control Signals Introduction Bus Arbitration Signals Coprocessor Interface Signals Interrupt Signals Signal Summary Memory and 1/0 Spaces BEO# Memory and 110 Organization Dynamic Data Bus Sizing Interfacing with 32- and 16-Bit Memories Cycles 1 and 1a Operand Alignment BEO# BHE# BLE# AD Li,\~~ P1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1 Address Pipelining ·9.Fastest Read Cycles with Pipelined Address Timing FOUR-BANK Interleaved Memory Address signal A2 selects bank Bit datapath to each bankTWO-BANK Interleaved Memory Read and Write Cycles Introduction Xxxi Xxxix NON-PIPELINED AddressXxxxx Ixxxx Ixxx 13 80386 Bus States not usIng pipelined address 3.3 NON·PIPELINED Address with Dynamic Data BUS Sizing ·14Asserting BS16# zero wait states, non·pipelinedaddress ~~~~ DOO¥ Xixxxxx ValidXixxxx ,XXXXY BSI6# XXX XXx XXX X .. IXXXXwOO~ J, XXX XXX1/ \ B516# ~~..tJ.~~~~~~~ BS16 # 44~~~...l-.lI...l Ready # 44~~.lI...l/l Bus Sizing with Pipelined Address Acknowledge ~ ,T1-T~-T2PJ ,T1PT2PJ Idle non-pipelined pipelinedPipelined IO#, D/c# Ffi 20 Complete Bus States including pipelined address Xxixxy ~ /..XIXXY Xxxxy ~j XDONTCAR~X~ x~ ~X~~lKX~ /..XXXXXxxxx IXXXXIXXXXI.. /..DXXXIXXX ~ Xxxxiy ~ -XXIXXY Interrupt Acknowledge Inta Cycles ~--cp--- ----- ----- ----- ----- ~ Halt Indication Cycle 23.Halt Indication Cycle Shutdown Indication Cycle 24. Shutdown Indication Cycle Other Functional Descriptions Reset During Hold AcknowledgeBus Activity During and Following Reset Entering and Exiting Hold Acknowledge 26. Requesting Hold from Active Bus NA # negated SELF-TEST Signature Component and Revision Identifiers Component Revision Component Revision Stepping Identifier Name Software Testing for Coprocessor Presence CMD1 Mechanical Data Introduction PIN Assignment 000 0 0 0 000 0 0 Vee Vss Package Dimensions and Mounting 1654189~1 Package Thermal Specification Measure PGA Case Temperature Infef80386 Ill Power and Grounding Electrical Data D.C. Specifications Maximum Ratings 102 A.C. Specifications1 A.C. Spec Definitions Unit Min Max Operating Frequency MHz Half of CLK2 2 A.C. Specification Tables·4 -16 A.C. Characteristics Symbol Parameter 80386-16 80386-16 Min Unit Max 16 A.C. Characteristics Symbol ParameterSymbol Parameter Min 3 A.C. Test Loads 4 A.C. Timing Waveforms 80386 ~QW~OOg OOOIP@OOIMl~iiO@OO 106 MAX Itm PI~ Instruction SET 80386 Instruction Encoding 8o386Instructlon Set CIock Count Summary 111 ·1 Instruction Set Clock Count Summary 112 80386 Instructlon Set CIockCount S ummary Contlnued RIm ·1 80386 Instruction Set Clock Count Summary Doubleword Instruction Set Clock Count Summary 115 Instruction Set Clock Count Summarycontlnued BIT Manipulation Instruction Set Clock Count Summar +ml 7+ml 80386 Ins ruefIon SetCIoek CountSummary ConrInued Protected 119 120 80386 Instructlon Set CIockCountSummaay Contmued Interrupt Instructions O3861nstructlon Set CIockCount Summary Contlnued Bound Infef80386 80386 nstructlon Set CIockCount Summary Contlnued Ns ruetIon StCIe oekCount 5 ummary Contlnued Madear Overview ~~~\ Field 2 32-Bit Extensions of the Instruction SetEncoding of Instruction Fields Bits Encoding of Address Mode 11010 OsbxOSBX+d16 EOI OS EAX Scale Factor NB/AE Encoding of Operation DirectionNAE NE/NZ Domestic Sales Offices California United States