Component Revision | Intel 80386 specs

intJ80386

	I----RESET		INTERNAL	+l	CYCLE 1
	I----RESET		----I---INITIALIZATION-----	+l
	~ 15 ClK2 DURATION IF
	NOT GOING TO REQUEST				NON-PIPELINED
	SELF-TEST.				NON-PIPELINED
	SELF-TEST.					(READ)
						(READ)
					T1	T2
ClK2[
RESET [
(FROM 82384)
ClK (INTERNAL) [
(82384ClK) [
9USY# [
ERROR# [
9EO#-9E3#.		DURING RESET
W/R#.M/IO#. [		DURING RESET
HlDA
A2-A31. [		DURING RESET
D/C#. lOCK#	~~_~_	DURING RESET
D/C#. lOCK#	~~_~_
ADS#[	~~~~	DURING RESET
ADS#[	~~~~
NA#[ ~~~~~~~~~~~~I.CI~~~~~~~
READY#[
00-031 # [	XXXXXXX> ---		-(FLOATING) - - - - - - - - - --

231630-32

NOTE 1:

BUSY # should be held stable for B CLK2 periods before and after the CLK2 period in which RESET falling edge occurs.

Figure 5-28. Bus Activity from Reset Until First Code Fetch

Table 5-10. Component and Revision Identifier History

	80386	Component	Revision	80386	Component	Revision
	Stepping			Stepping
		Identifier	Identifier		Identifier	Identifier
	Name			Name

92

Image 153

Intel 80386 manual Component Revision Stepping Identifier Name

Contents

Page Inter Intel Corporation Table of Contents Chapter Architectural Compatibility Chapter Highlights Page High-performance Implementation 32-bit Architecture Highlights Configurable Protection Virtual Memory SupportExtended Debugging Support Summary Object Code Compatibility Application Architecture Page Registers General RegistersFlags and Instruction Pointer Numeric Coprocessor Registers Memory and logical Addressing Logical Address Translation Segment and Descriptor Registers Addressing Modes Principal Data Types Data Types and Instructions Numeric Coprocessor Data Types Other InstructionsStack Instructions ~.,...I-------.-1 Byte String LII Miscellaneous Instructions Chapter System Architecture Page Multitasking System Registers Task State Segment Task Switching Address Translation Overview Addressing Address Translation Overview Segments Principal Descriptor Fields ~~~~~.II~~~ Pages Linear to Physical Address Translation Virtual Memory I I I Privilege Protection USing Privilege Levels Segment Protection Privileged Instructions Protection 10. Gates as Protected Entry Points Interrupts and Exceptions Interrupt Descriptor Table Debug Eceptions and Registers System Architecture Page Architectural Compatibility Page Real and Virtual 86 Modes 80286 Compatibility Architectural Compatibility Trapping Virtual 861\11ode System Calls Page Chapter Hardware Implementation Page Chapter Hardware Implementation Hardware Implementation Data and Address Buses Clock Bus Cycle Control Bus Cycle Definition Non-pipelined Bus Cycle Timing Bus Cycles with Pipelined Addresses Dynamic Bus Sizing Processor Status and ControlCoprocessor Control Mixed 16- and 32-bit Accesses Chapter Data Sheet Page 80386 Update Notice Table of Contents Interrupt Descriptor Table Descriptor Tables IntroductionSegment Descriptor Cache Privilege Validation Functional Data 3.4 Package Thermal SpecificationInitiating and Maintaining Pipelined Address Pipelined Address with Dynamic Data Bus Sizing Register Overview Base Architecture Introduction General Purpose Registers Register DescriptionsInstruction Pointer Flags Register TSS Segment Registers Segment Registers Descriptor Registers Loaded AutomaticallyOther Segment Physical Base Address Segment Limit Control Registers Segment Descriptor RegistersFlects the current state of the ET bit MSW Fault Linear Address Register CR2 TS Task Switched, bitSystem Address Registers Directory Base Register CR3 Register Accessibility Debug and Test RegistersCompatibility Iopl Instruction Set OverviewGdtr Idtr 2dLogical Instructions 2 80386 Instructions2a Data Transfer 2b Arithmetic Instructions 2f. Program Control Instructions 2e Bit Manipulation Instructions2g High Level Language Instructions 2h Protection Model Addressing Modes Overview Register and Immediate Modes3 32-Bit Memory Addressing Modes Differences Between 16 and 32 Bit Addresses Addressing Mode Calculations Data Types DisplacementBase Register BX,BP Index Register SI,DI Scale Factor None Sign ED rrrrrrrrl LilliililillIl Memory Organization IntroductionAddress Spaces Segment Register Usage I/O Space Interrupts and Ecep~ions InterruptsInterrupt Processing Maskable Interrupt Software Interrupts Non-Maskable Interrupt NMI 2.INTR Interrupt and Exception Priorities Reset and Initialization Double FaultInstruction Restart Testability TLB TestingSelf-Test Debugging Support Breakpoint Instruction Single-Step TrapDebug Registers DR2 DR1DR3 DR4 Usage Encoding Causing Breakpoint Debug Status Register DR6 Real Mode Architecture Real Mode Introduction Memory Addressing SET/RESET/COMPLEMENTXchg ADD, OR, ADC, SBB Reserved Locations IntierruptsShutdown and Halt Addressing Mechanism Protected Mode Addressing Terminology Segmentation IntroductionDescriptor Tables Descriptor Tables Introduction Byte DescriptorsAddress Segment Base 15 Segment Limit 15 Dptm typ , data gm,nt System Descriptor Formats Offset 15 SelectorWord Offset 31 Segment Base 15 Differences Between 386 and 286 DescriptorsSelector Fields Segment Descriptor Cache Nil R~L ~~~~~~~EL~~E~ ~A~~ ~I~I! ttl ~!~~~~E L~~E~~~s~ I~I! ~ J ~~?~~~~EL~~E~B~~E ~I~I~ tJ1 Protection Concepts Rules of PrivilegePrivilege Levels Privilege Level Transfers Call GOT/LOTRET,IRET CALL, JMP 80386 Call Ga~es Task Switching Infef Initialization and Transition to Protected Mode Paging Tools for Building ProtectedSystems Paging Concepts Mechanism Paging OrganizationDescriptor Base Register Directory Frame Address 31 Reserved Level Protection R/W, U/S BitsTables DIRECTORY/TABLE Entries Paging Operation Translation Lookaside Buffer Access Type Paging In Virtual ModeVirtual 8086 Environment Executing 8086 Programs 24. Virtual 8086 Environment Memory Management Protection and 1/0 Permission Bitmap Entering and Leaving Virtual Interrupt Handling Task Switches TO/FROM Virtual 8086 Mode For state saving i.e. push all registers in prolog, pop ·25.Virtual 8086 Environment Interrupt and Call Handling Clock CLK2 Introduction Address Bus BEO# through BE3#, A2 through A31 Data Bus do through Bus Cycle Definition Signals W/R#, D/C#, MIIO#, LOCK# Introduction Bus Control Signals Coprocessor Interface Signals Bus Arbitration Signals Interrupt Signals Signal Summary BEO# Memory and 1/0 Spaces Dynamic Data Bus Sizing Memory and 110 Organization Cycles 1 and 1a Interfacing with 32- and 16-Bit Memories BEO# BHE# BLE# AD Operand Alignment Li,\~~ P1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1 ·9.Fastest Read Cycles with Pipelined Address Timing Address Pipelining Address signal A2 selects bank Bit datapath to each bank TWO-BANK Interleaved MemoryFOUR-BANK Interleaved Memory Introduction Read and Write Cycles Xxxxx Ixxxx NON-PIPELINED AddressXxxi Xxxix Ixxx 13 80386 Bus States not usIng pipelined address ·14Asserting BS16# zero wait states, non·pipelinedaddress 3.3 NON·PIPELINED Address with Dynamic Data BUS Sizing Xixxxx ,XXXXY Xixxxxx Valid~~~~ DOO¥ BSI6# XXX XXx XXX X .. IXXXXwOO~ J, XXX XXX1/ \ B516# ~~..tJ.~~~~~~~ Bus Sizing with Pipelined Address BS16 # 44~~~...l-.lI...l Ready # 44~~.lI...l/l ~ ,T1-T~-T2PJ ,T1PT2PJ Idle non-pipelined pipelined PipelinedAcknowledge IO#, D/c# 20 Complete Bus States including pipelined address Ffi Xxxxx IXXXXIXXXXI.. /..DXXXIXXX ~ Xxxxiy Xxxxy ~j XDONTCAR~X~ x~ ~X~~lKX~ /..XXXXXxixxy ~ /..XIXXY ~ -XXIXXY ~--cp--- ----- ----- ----- ----- ~ Interrupt Acknowledge Inta Cycles 23.Halt Indication Cycle Halt Indication Cycle 24. Shutdown Indication Cycle Shutdown Indication Cycle Bus Activity During and Following Reset Reset During Hold AcknowledgeOther Functional Descriptions Entering and Exiting Hold Acknowledge 26. Requesting Hold from Active Bus NA # negated Component and Revision Identifiers SELF-TEST Signature Component Revision Stepping Identifier Name Component Revision CMD1 Software Testing for Coprocessor Presence PIN Assignment Mechanical Data Introduction 000 0 0 0 000 0 0 Vee Vss 1654189~1 Package Dimensions and Mounting Measure PGA Case Temperature Package Thermal Specification Ill Infef80386 Electrical Data Power and Grounding Maximum Ratings D.C. Specifications A.C. Specifications 1 A.C. Spec Definitions102 2 A.C. Specification Tables ·4 -16 A.C. Characteristics Symbol Parameter 80386-16Unit Min Max Operating Frequency MHz Half of CLK2 16 A.C. Characteristics Symbol Parameter Symbol Parameter Min80386-16 Min Unit Max 80386 ~QW~OOg OOOIP@OOIMl~iiO@OO 3 A.C. Test Loads 4 A.C. Timing Waveforms 106 MAX Itm PI~ 80386 Instruction Encoding Instruction SET 111 8o386Instructlon Set CIock Count Summary 112 ·1 Instruction Set Clock Count Summary RIm 80386 Instructlon Set CIockCount S ummary Contlnued Doubleword ·1 80386 Instruction Set Clock Count Summary 115 Instruction Set Clock Count Summary BIT Manipulation Instruction Set Clock Count Summarycontlnued +ml 7+ml Instruction Set Clock Count Summar Protected 80386 Ins ruefIon SetCIoek CountSummary ConrInued 119 120 Interrupt Instructions 80386 Instructlon Set CIockCountSummaay Contmued Bound O3861nstructlon Set CIockCount Summary Contlnued 80386 nstructlon Set CIockCount Summary Contlnued Infef80386 Madear Ns ruetIon StCIe oekCount 5 ummary Contlnued ~~~\ Overview Encoding of Instruction Fields 2 32-Bit Extensions of the Instruction SetField Bits Encoding of Address Mode OSBX+d16 Osbx11010 EOI OS EAX Scale Factor NAE Encoding of Operation DirectionNB/AE NE/NZ California Domestic Sales Offices United States