Intel DBPXA210 Intel BBPXA2xx Development Baseboard, UCB1400 Generates Interrupts Incorrectly

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Intel® BBPXA2xx Development Baseboard

Intel® BBPXA2xx Development Baseboard

10.UCB1400 Generates Interrupts Incorrectly

Problem:

The Philips UCB1400 interrupt signal is inverted.

Implication:

The UCB1400 generates interrupts incorrectly.

Workaround:

Reprogram FPGA U53/U54 with latest code. Refer to http://developer.intel.com for latest FPGA

 

updates.

Status:

Fixed

Board Rev:

Rev A and B

11.USB Cable Attach/Detach Detection Interrupt Is Constantly Asserted

Problem: Due to the hardware implementation of the USB cable detection feature, either the attach or detach interrupt is constantly asserted depending on the attach or detach state of the cable.

Implication: Software does not know if there is a connect or disconnect. Incorrect USB state can be read

Workaround: Perform the following steps to fix the problem.

1.Replace U12, MAX6348XR40 with MAX6379XR44.

2.Update U53/U54 with the latest code. Refer to http://developer.intel.com for latest FPGA updates.

 

One bit was added in the Miscellaneous Read register, bit 9, for cable detection state. Bit 9: logic

 

low = attach, logic high = detach. There are now two interrupt register bits both in the Interrupt

 

Mask/Enable and Interrupt Set/Clear registers to handle USB cable attach/detach states. Bit 2 is the

 

interrupt bit for attach and bit 6 is the interrupt bit for detach in both registers. Users must use each

 

register’s associated mask-bit accordingly. That is, users cannot clear the attach interrupt register if

 

the USB cable is attached. Users must determine the state of the cable attach using bit 9 in the

 

Miscellaneous Read register and then mask the associated interrupt bit in the Interrupt Mask/

 

Enable register. Refer to the Intel® DBPXA250 and DBPXA210 Development Platforms for Intel®

 

Personal Internet Client Architecture User’s Guide for more information.

Status:

Fixed

Board Rev:

Rev A and B

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DBPXA250 and DBPXA210 Development Platforms Specification Update

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Contents July Page Page Page Revision History Date Version DescriptionPreface Affected Documents/Related DocumentsNomenclature General Information Intel DCPXA250 Processor Card MarkingsSummary of Changes Codes Used in Summary TableECO no Summary of DCPXA210 Processor Card ECOs Sheet 2 Intel BBPXA2xx Development Baseboard UCB1400 Generates Interrupts IncorrectlyMHz Sdram Failure LCD Touch Screen Intermittently FailsLCD Picture Conditional ECO To Use 3.3-V Pcmcia Cards Conditional ECO To Use The Expansion Port J26Conditional ECO For USB Soft Connect Support Intel DCPXA250 Processor Card Vccpll And Vcccore Pin Voltage Must Be EqualMHz Sdram Requires 0-ohm Resistors Wire From The J3-3 To The Via Of U1 Pin For ARM* Multi-ICE* Jtag UseExcessive Oscillator Output Voltage to Pextal Pin Voltage DividerCoin Cell Battery Issue Signal Integrity Problems On SdclkVCC Core Voltage Change Intel DCPXA210 Processor Card For Multi-ICE Jtag UseMMC Mmclk Support PLL Voltage Too HighRemove Coin Cell Battery Incorrect Boot Mode Selected For PXA210 ProcessorIntel DCPXA210 Processor Card