CAS Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on the DRAM timing. The settings are: 2T and 2.5T.
AGP Timing Settings |
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| CMOS Setup Utility – Copyright(C) | |||
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| AGP Timing Settings |
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| AGP Transfer Aperture Size | 64M |
| Item Help | |
| AGP Transfer Mode | 4X |
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| AGP Driving Control | Auto |
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| * AGP Driving Value | DA |
| Menu Level >> | |
| AGP Fast Write | Disabled |
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| AGP Master 1 WS Write | Enabled |
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| AGP Master 1 WS Read | Enabled |
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| CPU to AGP Post Write | Disabled |
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| AGP Delay Transaction | Disabled |
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| AGP Delay Transaction | Disabled |
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| ↑↓→← Move Enter:Select | ESC:Exit F1:General Help | ||
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| F5:Previous Values | F6:Optimized Defaults | F7:Standard Defaults | |
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Note: | Change these settings only if you are familiar with the chipset. |
PCI Timing Settings |
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| CMOS Setup Utility – Copyright(C) | ||||
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| PCI Timing Settings |
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| PCI Master 1 | WS Write | Disabled |
| Item Help | |
| PCI Master 1 | WS Read | Disabled |
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| CPU to AGP Post Write | Enabled |
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| PCI Delay Transaction | Disabled |
| Menu Level >> | ||
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| ↑↓→← Move Enter:Select | ESC:Exit F1:General Help | |||
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| F5:Previous Values | F6:Optimized Defaults | F7:Standard Defaults | ||
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PCI Delay Transaction
The chipset has an embedded
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