8xC251Tx Hardware Description
3.2Special Function Register Definitions
The following describes the special function registers associated with the second serial I/O port and their bit definitions.
3.2.1SCON1
Address: 9AH
Reset Value: 0000 0000B
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| Table 6. SCON1 Special Function Register Definitions |
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Bit Number | Bit |
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Mnemonic |
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7 | FE1SM0 |
| Framing Error Bit 1: |
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| To Select this function, set the SMOD0 bit in the BGCON register. Set by hard- | ||||
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| ware to indicate an invalid stop bit. Cleared by software, not by valid frames | ||||
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| Second Serial I/O Port Mode Bit 0: |
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| To select this function, clear the SMOD0 bit in the BGCON register. Software | ||||
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| writes to bit SM0 and SM1 to select the second serial I/O port operating | ||||
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| mode. Refer to SM1 bit for mode selections |
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6 | SM1 |
| Second Serial I/O Port Mode Bit 1: |
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| Software write to bit SM0 and SM1 (above) to select the serial port operating | ||||
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| mode. |
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| SM0 | SM1 | Mode | Description | Baud Rate |
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| 0 | 0 | 0 | Shift Register | Fosc/12 |
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| 0 | 1 | 1 | 8 bit UART | variable |
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| 1 | 0 | 2 | 9 bit UART | Fosc/32* or Fosc/64* |
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| 1 | 1 | 3 | 9 bit UART | variable |
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| * Select by programming the SMOD0 bit in the BGCON register | ||||
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5 | SM2 |
| Second Serial I/O Port Mode Bit 2: |
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| Software writes to SM2 enable and disable the multiprocessor communica- | ||||
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| tion and automatic address recognition features. This allows the second | ||||
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| serial I/O port to differentiate between data and command frames and to rec- | ||||
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| ognize slave and broadcast addresses |
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4 | REN1 |
| Receive Enable Bit 1: |
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| To enable reception, set this bit. To enable transmission, clear this bit | ||||
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3 | TB8 |
| Transmit Bit 8: |
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| In modes 2 and 3, software writes the ninth data bit to be transmitted to TB8. | ||||
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| Not used in modes 0 and 1 |
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2 | RB8 |
| Receive Bit 8: |
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| Mode 0: not used |
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| Mode 1 (SM2 clear): Set or cleared by hardware to reflect the stop bit | ||||
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| received |
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| Modes 2 and 3 (SM2 set): Set or cleared by hardware to reflect the ninth | ||||
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| data bit received |
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1 | TI1 |
| Second Serial I/O Port Transmit Interrupt Flag Bit: |
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| Set by transmitter after the last data bit is transmitted. Cleared by software | ||||
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0 | RI1 |
| Second Serial I/O Port Receive Interrupt Flag Bit: |
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| Set by the receiver after the last data bit of a frame has been received. | ||||
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| Cleared by software |
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| 9 |
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