Intel 8XC251SA, 8xC251TB, 8XC251SP, 8XC251SQ Summary of the EDF# and WSB#10 Configuration Options

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8xC251Tx Hardware Description

Table 13 shows the effect of programming EDF# and WSB#[1:0] on the extended data float timing feature as well as the insertion of wait states for region 01:. It should be noted that enabling the extended data float timing allows region 01: to have 1 or 3 wait states inserted (depending on WSB#[1:0]) but not 0 or 2 wait states.

Table 13. Summary of the EDF# and WSB#[1:0] Configuration Options

	EDF#	WSB#[1:0]	Wait State	Extended Data Float
	EDF#	WSB#[1:0]	Wait State	Timings
				Timings

	1	11	0	No

	1	10	1	No

	1	01	2	No

	1	00	3	No

	0	11	1	Yes

	0	10	1	Yes

	0	01	3	Yes

	0	00	3	Yes

The external user configuration cycle (UCONF = 1 and EA# = 0) will be executed with the extended TRHDZ1 timing bus cycle.

13

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Contents 8xC251TB, 8xC251TQ, Hardware Description Page Description DateDecember 273138-002 8xC251TB, 8xC251TQ Hardware Description 8xC251Tx Hardware Description OTPROM/EPROM XC251Tx Block DiagramProcessor Control Name XC251Tx Signal SummaryPower & Ground Name Address & Data NameSignal Type Description Alternate Name Function XC251Tx Signal Descriptions Sheet 1Address Line 16. See RD# Timer 10 External Clock Inputs. When Timer 10 operates as a XC251Tx Signal Descriptions Sheet 2GND XC251Tx Signal Descriptions Sheet 3Signal Description Alternate Name FunctionCH00000 CCAP0Hx CCAP1Hx CCAP2Hx CCAP3Hx CCAP4Hx Xxxxxxx Special Function Register SFR MapFunction Type Description Multiplexed Second Serial I/O Port SignalsMnemonic Description Address Second Serial I/O Port Special Function RegistersBit Number Function Mnemonic Bit Number Bit Mne Function Monic IPH1.0 IPL1.0 Priority Level Bit NumberExtended Data Float Timings UCONFIG1 bit definitions for the 8xC251TxInterrupt Mode Reserved for Internal or Future UseWSB#10 Wait State Extended Data Float Summary of the EDF# and WSB#10 Configuration Options

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