Intel 8XC251SP Second Serial I/O Port Special Function Registers, Mnemonic Description Address

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8xC251Tx Hardware Description

Table 5. Second Serial I/O Port Special Function Registers

Mnemonic

Description

Address

 

 

 

SBUF1

Serial Buffer 1. Two separate registers comprise the SBUF1 register. Writ-

9BH

 

ing to SBUF1 loads the transmit buffer; reading SBUF1 access the receive

 

 

buffer

 

 

 

 

SCON1

Serial Port Control 1. Selects the second serial I/O port operating mode.

9AH

 

SCON1 enables and disables the receiver, framing bit error detection, multi-

 

 

processor communication, automatic address recognition and the serial port

 

 

interrupt bits.

 

 

 

 

SADDR1

Serial Address 1. Defines the individual address for a slave device

AAH

 

 

 

SADEN1

Serial Address Enable 1. Specifies the mask byte that is used to define the

BAH

 

given address for a slave device

 

 

 

 

BGCON

Secondary Serial Port Control. Contains controls to the second serial port

8FH

 

including the double baud rate bit, read/write access to the SCON1.7 bit as

 

 

well as bits to control Timer1 or 2 overflow as the baud rate generator for

 

 

reception and transmission

 

 

 

 

IE1

Interrupt Enable Register 1. Contains the second serial I/O port interrupt

B1H

 

enable bit

 

 

 

 

IPL0

Interrupt Priority Low Control Register 1. IPL0, together with IPH0,

B2H

 

assigns the second serial I/O port interrupt level from 0 (lowest) to 3 (high-

 

 

est)

 

 

 

 

IPH0

Interrupt Priority High Control Register 1. IPH0, together with IPL0,

B3H

 

assigns the second serial I/O port interrupt level from 0 (lowest) to 3 (high-

 

 

est)

 

 

 

 

The second serial I/O port interrupt is enabled by setting the ES1 bit in the IE1 register. The priority of the second serial I/O port’s interrupt is set to one of four levels by programming the IPL1.0 and IPH1.0 bits in the IPL1 and IPH1 registers, respectively. The second serial I/O port is last in the interrupt polling sequence (see Chapter 6 of the 8xC251SA, 8xC251SB, 8xC251SP, 8xC251SQ Embedded Microcontroller User’s Manual (272795) for details of the interrupt system). The second serial I/O port's Interrupt Service Routine Vector Address is FF:0043H.

When the second serial I/O port is used, the alternate functions of RXD1 and TXD1 can no longer be used. Specifically, the PCA can no longer be clocked by an external clock input since ECI now functions as RXD1. The PCA can, however, be clocked by one of three other methods. They consist of two fixed frequencies (fixed in relation to the Oscillator frequency); FOSC/12 and FOSC/4 and Timer 0 overflow.

The other consequence of using the second serial I/O port is Module 0 of the PCA can now be used only as a 16 bit Software Timer. The 16-bit Capture, High Speed Output and Pulse Width Modulation modes are no longer available to Module 0 as these modes require the use of CEX0 (which, when the second serial I/O port is in operation, functions as TXD1).

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Contents 8xC251TB, 8xC251TQ, Hardware Description Page Date DescriptionDecember 273138-002 8xC251TB, 8xC251TQ Hardware Description 8xC251Tx Hardware Description XC251Tx Block Diagram OTPROM/EPROMAddress & Data Name XC251Tx Signal SummaryPower & Ground Name Processor Control NameAddress Line 16. See RD# XC251Tx Signal Descriptions Sheet 1Signal Type Description Alternate Name Function XC251Tx Signal Descriptions Sheet 2 Timer 10 External Clock Inputs. When Timer 10 operates as a Description Alternate Name Function XC251Tx Signal Descriptions Sheet 3 Signal GNDSpecial Function Register SFR Map CH00000 CCAP0Hx CCAP1Hx CCAP2Hx CCAP3Hx CCAP4Hx XxxxxxxSecond Serial I/O Port Signals Function Type Description MultiplexedSecond Serial I/O Port Special Function Registers Mnemonic Description AddressBit Number Function Mnemonic Bit Number Bit Mne Function Monic Bit Number IPH1.0 IPL1.0 Priority LevelReserved for Internal or Future Use UCONFIG1 bit definitions for the 8xC251TxInterrupt Mode Extended Data Float TimingsSummary of the EDF# and WSB#10 Configuration Options WSB#10 Wait State Extended Data Float
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