L3 Cache Copy Tag
The data residing in caches and main memory across Intel Itanium Server Blades are kept in sync by using a snooping cache coherency protocol. When one of the Intel Itanium processors needs to access memory, the requested address is broadcast by the Hitachi Node Controller. The other Node Controllers that are part of that partition (SMP) listen for (snoop) those broadcasts. The Node Controller keeps track of the memory addresses currently cached in each processor’s
| Node 0 | Node 1 |
| ||
Itanium2 | Itanium2 | Itanium2 | Itanium2 | ||
L3 C |
| (1) | (2) | (3)’ | L3 C |
Copy | Node | Node | Copy | ||
Tag | Tag | ||||
| Controller | Controller |
| ||
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|
| (4) | (3) | |
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|
|
|
| |
Memory | Memory | Memory | Memory | ||
Controller | Controller | Controller | Controller | ||
| Main Memory | Main Memory |
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(1)Cache consistency control within a local node
(2)Memory address
broadcasting
(3) | Parallel | (3)’ Cache |
consistency | ||
Memory | Processing | control over |
access |
| remote nodes |
|
|
(4)Memory data transfer or
Cache data transfer
Figure 10. L3 cache copy tag process
Intel Itanium I/O Expansion Module
Some applications require more PCI slots than the two that are available per server blade. The Intel Itanium I/O Expansion Module provides more ports, without the expense of additional server blades. Using the Itanium I/O Expansion Module with the Intel Itanium Server Blade can increase the number of the PCI
The Intel Itanium I/O Expansion Module increases the number of PCI I/O slots to either four or eight slots depending on the chassis type. The type A chassis enables connection to four PCI I/O slots (Figure 11), and the type B chassis enables up to eight PCI I/O slots (Figure 12).
18 BladeSymphony 1000 Architecture White Paper | www.hitachi.com |