Z990 Design and Technology

To support the new scalability of the z990 a new improve- ment to the I/O Subsystem has been introduced to “break the barrier” of 256 channels per Central Electronic Com- plex (CEC). This provides “horizontal” growth by allowing the deﬁ nition of up to four Logical Channel SubSystems each capable of supporting up to 256 channels giving a total of up to 1024 CHPIDs per CEC. The increased scal- ability is further supported by the increase in the number of Logical Partitions available from the current 15 LPARs to a new 30 LPARs. There is still a 256-channel limit per oper- ating system image.

These are some of the signiﬁ cant enhancements in the zSeries 990 server that bring improved performance, avail- ability and function to the platform. The following sections highlight the functions and features of the server.

z990 Design and Technology

The z990 is designed to provide balanced system perfor- mance. From processor storage to the system’s I/O and network channels, end-to-end bandwidth is provided and designed to deliver data where and when it is needed.

The z990 provides a signiﬁ cant increase in system scal- ability and opportunity for server consolidation by pro- viding four models, from one to four MultiChip Modules (MCMs), delivering up to a maximum 32-way conﬁ gura- tion. The MCMs are conﬁ gured in a book package, with each book comprised of a MultiChip Module (MCM), memory cards and Self-Timed Interconnects. The MCM, which measures approximately 93 x 93 millimeters (42%

smaller than the z900), contains the processor unit (PU) chips, the cache structure chips and the processor stor- age controller chips. The MCM contains 101 glass ceramic layers to provide interconnection between the chips and the off-module environment. In total, there is approximately

0.4kilometer of internal copper wiring on this module. This new MCM packaging delivers an MCM 42% smaller than the z900, with 23% more I/O connections and 133% I/O density improvement. Each MCM provides support for 12 PUs and 32 MB level 2 cache. Each PU contains 122 million transistors and measures 14.1 mm x 18.9 mm. The design of the MCM technology on the z990 provides the ﬂ exibility to conﬁ gure the PUs for different uses; two of the PUs are reserved for use as System Assist Processors (SAPs), two are reserved as spares. The remaining inac- tive 8 PUs on the MCM are available to be characterized as either CPs, ICF processors for Coupling Facility appli- cations, IFLs for Linux applications, IBM ^zSeries Application Assist Processor (zAAPs) for Java applications or as optional SAPs, providing the customer with tremen- dous ﬂ exibility in establishing the best system for running applications. Each model of the z990 must always be ordered with at least one CP, IFL or ICF.

The PU, which uses the latest chip technology from IBM semiconductor laboratories, is built on CMOS 9S-SOI with copper interconnections. The 14.1 mm x 18.9 mm chip has a cycle time of 0.83 nanoseconds. Implemented on this chip is the z/Architecture with its 64-bit capabilities includ- ing instructions, 64-bit General Purpose Registers and translation facilities.