
THEORY OF OPERATION
2-4.  Power-On  Reset Circuit
Immediately following 
+
C2
| 
 | +5V | 
| IC4 | +5V | 
| 
 | |
| 
 | VCC | 
| CD | RESET | 
| 
 | GND | 
RESET IC
IC5 : CPU
CPU
 RESRESO
 RESRESO 
DD3
Circuit
+5V
+5V
VCC
IC10
RESET
Gate array
IC1
Fig. 2-10  Power-On  Reset Circuit
1At power on, voltage-detector  circuit IC4 (M51953BL) outputs a LOW signal from its OUT terminal. The signal lasts for approximately 160ms, as determined by capacitor C2 (0.47μF):
T = 0.34 × C2 (pF) [μs] = 160ms
2The LOW signal resets the CPU and the mechanism drive circuits, and sets S-RAM  into backup state.
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