Fujitsu MB39A105 manual Timer-latch short-circuit protection circuit

MB39A105

■SETTING TIME CONSTANT FOR TIMER-LATCH SHORT-CIRCUIT PROTECTION CIRCUIT

The error amplifier’s output level alaways does the comparison operation with the short-circuit protection com- parator (SCP Comp.) to the reference voltage.

While DC/DC converter load conditions are stable, the short-circuit detection comparator output remains stable, and the CSCP terminal (pin 2) is held at soft-start end voltage (about 0.8 V) .

If the load condition changes rapidly due to a short-circuit of the load and the DC/DC converter output voltage drops, the output of the error amplifier usually goes over 0.9 V. In that case, the capacitor CSCP is charged further. When the capacitor CSCP is charged to about 1.0 V, the latch is set and the external FET is turned off (dead time is set to 100%). At this time, the latch input is closed and the CSCP terminal (pin 2) is held at “L” level. When CSCP terminal becomes “L” level, SCPOD terminal Nch MOS FET becomes OFF. SCPOD terminal (pin 4) is held at “L” level and can be used as a short-circuit operating detection signal during normal operation.

To reset the actuated protection circuit, the power supply turn off and on again to lower the VCC terminal (pin

3)voltage to 1.1 V (Min) or less.

Short-circuit detection time (tCSCP) tCSCP (s) =: 0.23 ⋅ CSCP (∝F)

•Timer-latch short-circuit protection circuit

VO
FB	8
R1			Error
−INE
	1	−	Amp
		−
R2		+
		(0.5 V)
	(0.88 ∝A) (10.1 ∝A)	VREF
					SCP
					Comp.	−
						+	(0.9 V)
							to Drive
CSCP	2	−
		+
	(1.0 V)					VREF
			S	R
			Latch			UVLO

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