EM78P447N
NOTE
After waking up from the SLEEP2 mode, WDT is automatically enabled. The WDT enabled/disabled operation after waking up from SLEEP2 mode should be appropriately defined in the software.
To avoid reset from occurring when the port6 status changed interrupt enters into interrupt vector or is used to
Table 7 The Summary of the Initialized Values for Registers
| Address |
| Name |
| Reset Type |
| Bit 7 |
| Bit 6 |
| Bit 5 |
| Bit 4 |
| Bit 3 |
| Bit 2 |
| Bit 1 |
| Bit 0 |
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| Bit Name |
| C57 |
| C56 |
| C55 |
| C54 |
| C53 |
| C52 |
| C51 |
| C50 |
| |||||||||
| N/A |
| IOC5 |
| Type |
| A |
| B |
| A |
| B |
| A |
| B |
| A |
| B | - |
| - | - |
| - |
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| ||
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| 0 |
| 1 |
| 0 |
| 1 | 0 |
| 1 | 0 |
| 1 | 1 |
| 1 | 1 |
| 1 |
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| /RESET and WDT |
| 0 |
| 1 |
| 0 |
| 1 | 0 |
| 1 | 0 |
| 1 | 1 |
| 1 | 1 |
| 1 |
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| 0 | P |
| 0 | P | 0 | P | 0 | P |
| P |
| P |
| P |
| P |
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| Change |
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| N/A |
| IOC6 |
| Bit Name |
| C67 |
| C66 |
| C65 |
| C64 |
| C63 |
| C62 |
| C61 |
| C60 |
| |||||||||
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| 1 |
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| 1 |
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| 1 |
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| 1 |
| 1 |
| 1 |
| 1 |
| 1 |
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| /RESET and WDT |
|
| 1 |
|
| 1 |
|
| 1 |
|
| 1 |
| 1 |
| 1 |
| 1 |
| 1 |
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| P |
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| P |
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| P |
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| P |
| P |
| P |
| P |
| P |
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| Change |
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| N/A |
| IOC7 |
| Bit Name |
| C77 |
| C76 |
| C75 |
| C74 |
| C73 |
| C72 |
| C71 |
| C70 |
| |||||||||
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| 1 |
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| 1 |
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| 1 |
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| 1 |
| 1 |
| 1 |
| 1 |
| 1 |
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| /RESET and WDT |
|
| 1 |
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| 1 |
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| 1 |
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| 1 |
| 1 |
| 1 |
| 1 |
| 1 |
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| P |
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| P |
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| P |
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| P |
| P |
| P |
| P |
| P |
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| Change |
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| N/A |
| CONT |
| Bit Name |
| /PHEN |
| /INT |
|
| TS |
|
| TE |
| PAB |
| PSR2 |
| PSR1 |
| PSR0 |
| |||||||
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| 1 |
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| 0 |
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| 1 |
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| 1 |
| 1 |
| 1 |
| 1 |
| 1 |
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| /RESET and WDT |
|
| 1 |
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| P |
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| 1 |
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| 1 |
| 1 |
| 1 |
| 1 |
| 1 |
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| P |
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| P |
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| P |
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| P |
| P |
| P |
| P |
| P |
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| Change |
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| 0x00 |
| R0(IAR) |
| Bit Name |
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| - |
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| - |
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| - |
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| - | - |
| - | - |
| - |
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| U |
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| U |
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| U |
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| U |
| U |
| U |
| U |
| U |
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| /RESET and WDT |
|
| P |
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| P |
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| P |
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| P |
| P |
| P |
| P |
| P |
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| P |
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| P |
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| P |
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| P |
| P |
| P |
| P |
| P |
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| Change |
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| 0x01 |
| R1(TCC) |
| Bit Name |
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| - |
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| - |
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| - |
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| - |
| - |
| - |
| - |
| - |
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| 0 |
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| 0 |
|
| 0 |
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| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
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| /RESET and WDT |
|
| 0 |
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| 0 |
|
| 0 |
|
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
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| P |
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| P |
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| P |
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| P |
| P |
| P |
| P |
| P |
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| Change |
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| 0x02 |
| R2(PC) |
| Bit Name |
|
| - |
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| - |
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| - |
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| - |
| - |
| - |
| - |
| - |
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| ||||
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| 1 |
|
| 1 |
|
| 1 |
|
| 1 |
| 1 |
| 1 |
| 1 |
| 1 |
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| |||||||
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| /RESET and WDT |
|
| 1 |
|
| 1 |
|
| 1 |
|
| 1 |
| 1 |
| 1 |
| 1 |
| 1 |
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| ||||
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| **0/P |
| **0/P |
| **0/P |
| **0/P |
| **0/P |
| **0/P |
| **0/P |
| **0/P |
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| Change |
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| 0x03 |
| R3(SR) |
| Bit Name |
|
| GP |
| PS1 |
| PS0 |
|
| T |
| P |
| Z |
| DC |
| C |
| |||||||
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| 0 |
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| 0 |
|
| 0 |
|
| 1 |
| 1 |
| U |
| U |
| U |
| ||||||||
|
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| /RESET and WDT |
|
| 0 |
|
| 0 |
|
| 0 |
|
| t |
| t |
| P |
| P |
| P |
| |||||
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| P |
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| P |
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| P |
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| t |
| t |
| P |
| P |
| P |
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| Change |
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| 0x04 |
| R4(RSR) |
| Bit Name |
| RSR.1 |
| RSR.0 |
|
| - |
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| - |
| - |
| - |
| - |
| - |
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| ||||||
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| 0 |
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| 0 |
|
| U |
|
| U |
| U |
| U |
| U |
| U |
| ||||||||
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| /RESET and WDT |
|
| 0 |
|
| 0 |
|
| P |
|
| P |
| P |
| P |
| P |
| P |
| |||||
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Product Specification (V1.1) 03.30.2005 |
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| • 19 |
(This specification is subject to change without further notice)