Fujitsu MHV2040AS, MHV2080AS, MHV2060AS manual Terminating an Ultra DMA data out burst

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5.5 Ultra DMA Feature Set

5.5.4.4Terminating an Ultra DMA data out burst

a)Host terminating an Ultra DMA data out burst

The following stops shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.10 and 5.6.3.2 for specific timing requirements):

1)The host shall initiate termination of an Ultra DMA burst by not generating HSTROBE edges.

2)The host shall assert STOP no sooner than tSS after it last generated an HSTROBE edge. The host shall not negate STOP again until after the Ultra DMA burst is terminated.

3)The device shall negate DMARQ within tLI after the host asserts STOP. The device shall not assert DMARQ again until after the Ultra DMA burst is terminated.

4)The device shall negate DDMARDY- with tLI after the host has negated STOP. The device shall not assert DDMARDY- again until after the Ultra DMA burst termination is complete.

5)If HSTROBE is negated, the host shall assert HSTROBE with tLI after the device has negated DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition on HSTROBE. HSTROBE shall remain asserted until the Ultra DMA burst is terminated.

6)The host shall place the result of its CRC calculation on DD (15:0) (see 5.5.5)

7)The host shall negate DMACK- no sooner than tMLI after the host has asserted HSTROBE and STOP and the device has negated DMARQ and

DDMARDY-, and no sooner than tDVS after placing the result of its CRC calculation on DD (15:0).

8)The device shall latch the host's CRC data from DD (15:0) on the negating edge of DMACK-.

9)The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5).

10)The device shall release DDMARDY- within tIORDYZ after the host has negated DMACK-.

11)The host shall neither negate STOP nor negate HSTROBE until at least tACK after negating DMACK-.

12)The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK after negating DMACK.

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Contents Disk Drive Product Manual MHV2080AS, MHV2060AS, MHV2040ASHandling of This Manual For Safe OperationRevision History This page is intentionally left blank Overview of Manual PrefaceConventions Conventions for Alert MessagesOperating Environment Liability Exception This page is intentionally left blank Damage Interface cable connection Important Alert ItemsImportant Alert Messages This page is intentionally left blank Manual Organization Disk Drive Maintenance ManualMHV2080AS Disk Drive Product ManualThis page is intentionally left blank Contents Theory of Device Operation Installation ConditionsInterface Contents101 Write Multiple EXT X’39’ Option customizing Operations Glossary GL-1 Acronyms and Abbreviations AB-1 Index IN-1 Figures IllustrationsExecution example of Read Multiple command Examples of model names and product numbers Tables127 This page is intentionally left blank Device Overview Adaptability FeaturesFunctions and performance High resistance against shock Error correction and retry by ECCConnection to ATA interface Data bufferSpecifications summary Device SpecificationsSpecifications 1 MHV2080AS MHV2060AS MHV2040ASExamples of model names and product numbers Model and product numberRipple Power RequirementsInput Voltage Current and power dissipation Current Requirements and Power DissipationCurrent fluctuation Typ. at +5 V when power is turned on Environmental SpecificationsPower on/off sequence Environmental specificationsShock and vibration specification Acoustic noise specificationAcoustic Noise Shock and VibrationData assurance in the event of power failure Service lifeReliability Mean time between failures MtbfUnrecoverable read error Error RatePositioning error Media DefectsAdvanced Power Management Advanced Power Management This page is intentionally left blank Device Configuration Device Configuration ATA interface System Configuration2 1 drive connection Read/write circuit3 2 drives connection 2 drives configurationInstallation Conditions Dimensions DimensionsOrientation MountingIntegration Guidance C141-E144 PCA FrameLimitation of mounting Location of breather Ambient temperature Handling cautions Service areaHandling cautions Cable Connections Device connectorCable connector specifications Cable connector specificationsDevice connection FCILocation of setting jumpers Jumper SettingsPower supply connector CN1 Master drive-slave drive setting Factory default setting14 Csel setting Csel setting16 Example 2 of cable select Power up in standby settingTheory of Device Operation Subassemblies OutlineDisk SpindleAir filter Circuit ConfigurationServo circuit Spindle motor driver circuitPower supply configuration PCA Power-on operation sequence Power-on SequenceSelf-calibration Self-calibration contentsExecution timing of self-calibration Command processing during self-calibrationRead/write preamplifier PreAMP Read/write CircuitWrite circuit Write precompensationProgrammable filter circuit Read circuitAGC circuit FIR circuit Digital PLL circuitD converter circuit Viterbi detection circuitServo control circuit Servo ControlMicroprocessor unit MPU Power amplifierServo burst capture circuit A converter DACVCM current sense resistor CSR Driver circuitInner guard band Data-surface servo formatData area Outer guard bandPhysical sector servo configuration on disk surface Servo frame format Operation to move the head to the reference cylinder Actuator motor controlSeek operation Track following operationAcceleration mode Start modeStable rotation mode Spindle motor controlThis page is intentionally left blank Interface Physical Interface Interface signalsSignal assignment on the interface connector Signal assignment on the connectorDA1 PDIAG-, Cblid DA0 DA2 Dasp GNDDiow MstrStop DiorCblid PdiagDasp IordyLogical Interface DA2 DA1 DA0 1 I/O registersI/O registers Error register X’1F1’ Command block registersData register X’1F0’ UNC IdnfSector Count register X’1F2’ Features register X’1F1’Cylinder High register X’1F5’ Sector Number register X’1F3’Cylinder Low register X’1F4’ DEV HS3 HS2 HS1 HS0 Device/Head register X’1F6’Status register X’1F7’ BSYInterface Alternate Status register X’3F6’ Command register X’1F7’Control block registers Command code and parameters Host CommandsDevice Control register X’3F6’ HOB SrstParameter Used Command code and parameters 1Command Name EXT Write Multiple FUA EXT Flush Cache EXT Command code and parameters 2Host Commands Command descriptions Host Commands Recalibrate X’10’ to X’1F’ MSB Read Sectors X’20’ or X’21’End head No. / LBA MSB Write Sectors X’30’ or X’31’ 1F7HST Status information 1F6HDH Write Verify X’3C’ Read Verify Sectors X’40’ or X’41’ Seek X’70’ to X’7F’ Diagnostic code Execute Device Diagnostic X’90’Device responds to this command with the result of power-on Initialize Device Parameters X’91’ Download Microcode X’92’ Operation of Download Microcode Standby Immediate X’94’ or X’E0’ Unload Feature Unload Immediate Command Host Commands Standby X’96’ or X’E2’ Idle X’97’ or X’E3’ Interface ’FF’ Check Power Mode X’98’ or X’E5’Sleep X’99’ or X’E6’ Smart X’B0 Features register values subcommands and functions 1 Smart Enable Operations Features register values subcommands and functions 2Smart Disable Operations Smart Read LOGSmart Return Status Features register values subcommands and functions 3’DB’ Smart ENABLE/DISABLE Auto OFF-LINE Host Commands Format of insurance failure threshold value data Format of device attribute value data1FF Attribute ID Data format version numberCurrent attribute value Status FlagAttribute value for the worst case so far Raw attribute value11 Self-test execution status 10 Off-line data collection statusSelf-test execution status 12 Off-line data collection capability Off-line data collection capabilityFailure prediction capability flag 13 Failure prediction capability flag14 Error logging capability Error logging capabilityCheck sum Insurance failure thresholdSmart error logging 16 Data format of Smart Summary Error Log Error data structure Command data structureTotal number of drive errors 17 Data format of Smart Comprehensive Error Log18 Smart self-test log data format Smart self-test1FC Self-test numberTest span 19 Selective self-test log data structureCurrent LBA under test Current span under testSelective Self-test pending time min Feature Flags20 Selective self-test feature flags Device Configuration Restore Device Configuration XB1Device Configuration Freeze Device Configuration IdentifyDevice Configuration Freeze Lock FR = C1h Device Configuration Restore FR = C0hDevice Configuration Identify FR = C2h Device Configuration SET FR = C3hInterface 21 Device Configuration Identify data structure 1/2 21 Device Configuration Identify data structure 2/2 Read Multiple X’C4’ Execution example of Read Multiple commandMSB Write Multiple X’C5’ Interface SET Multiple Mode X’C6’ Interface Read DMA X’C8’ or X’C9’ End head No. / LBA MSB Write DMA X’CA’ or X’CB’ Interface Read Buffer X’E4’ Flush Cache X’E7’ Write Buffer X’E8’ Identify Device X’EC’ Identify Device DMA X’EE’ ’3FFF’ 22 Information to be read by Identify Device command 122 Information to be read by Identify Device command 2 3FFF Command without interrupt supports 2, 4, 8 and 16 sectors = Supports the Host Protected Area feature set = Supports the CFA Compact Flash Association feature set Interface Write Stream EXT Interface Host Commands Word Bit Reserved Security level High, 1 Maximum 23 Features register values and settable modes SET Features X’EF’’BB’ ’CC’Data Transfer Mode Advanced Power Management APM Automatic Acoustic Management AAM 24 Contents of Security SET Password data Interface Security UNLOCKX’F2’ When the master password is selectedWhen the user password is selected Interface Security Erase Prepare X’F3’ Security Erase Unit X’F4’ Security Freeze Lock X’F5’ Interface 26 Contents of security password Interface Read Native MAX Address X’F8’ SET MAX Address SET MAX X’F9’SET MAX SET Password FR = 01h SET MAX Lock FR = 02h SET MAX Unlock FR = 03h SET MAX Freeze Lock FR = 04h Host Commands Read Sectors EXT X’24’ Option customizing Description Read DMA EXT X’25’ Option customizing Description Error reporting conditions Read Multiple EXT X’29’ Option customizing Description Read LOG EXT X2F Optional command Customize Description Host Commands Write Sectors EXT X’34’ Option customizing Description Write DMA EXT X’35’ Option customizing Description SET MAX Address EXT X’37’ Option customizing Description SET MAX LBA Write Multiple EXT X’39’ Option customizing Description Write DMA FUA EXT X’3D’ Option customizing Description Write LOG EXT X’3F’ Optional command Customize Description Host Commands Read Verify Sectors EXT X’42 Option customizing Description Write Multiple FUA EXT X’CE’ Option customizing Description Flush Cache EXT X’EA’ Option customizing Description 27 Command code and parameters 1 Error posting27 Command code and parameters 2 Execute Device Diagnostic Initialize Device Parameters Command ProtocolPIO Data transferring commands from device to host Read Sectors Command protocol Protocol for command abort PIO Data transferring commands from host to device Write Sectors command protocol Commands without data transfer DMA data transfer commands Other commandsRead Multiple EXT Write Multiple EXT/FUA EXT Sleep Read DMA EXT Write DMA EXT/FUA EXT Indentify Device DMANormal DMA data transfer Overview Ultra DMA Feature SetInitiating an Ultra DMA data in burst Phases of operationUltra DMA data in commands Data in transfer Pausing an Ultra DMA data in burstTerminating an Ultra DMA data in burst Ultra DMA Feature Set Interface Initiating an Ultra DMA data out burst Ultra DMA data out commandsData out transfer Pausing an Ultra DMA data out burstTerminating an Ultra DMA data out burst Interface Ultra DMA CRC rules 28 Recommended series termination for Ultra DMA Series termination required for Ultra DMADIOR-HDMARDY-HSTROBE DIOW-STOPPIO data transfer timing TimingPIO data transfer Multiword data transfer 10 Multiword DMA data transfer timing mode11 Initiating an Ultra DMA data in burst Ultra DMA data transferStrobe Name Mode CommentMIN MAX 29 Ultra DMA data burst timing requirements 230 Ultra DMA sender and recipient timing requirements Mode Name CommentDstrobe at device Sustained Ultra DMA data in burstDD150 at device Dstrobe at host DD150 at hostDmarq Host pausing an Ultra DMA data in burstDmack HdmardyStop Device terminating an Ultra DMA data in burstDA0, DA1, DA2 CS0, CS1 Host terminating an Ultra DMA data in burstHost 16 Initiating an Ultra DMA data out burst Hstrobe at device DD150 at device Sustained Ultra DMA data out burstHstrobe at host DD150 at host Hstrobe host DD150 Host Device pausing an Ultra DMA data out burstDevice DMACK- host Stop host DDMARDY- device 19 Host terminating an Ultra DMA data out burst Host terminating an Ultra DMA data out burstDD150 Host Device terminating an Ultra DMA data out burstDmarq device DMACK- host Only master device is present Power-on and resetMaster and slave devices are present 2-drives configuration Operations Response to power-on Device Response to the ResetResponse to power-on Response to hardware resetResponse to hardware reset Response to software reset Response to software resetResponse to diagnostic command Response to diagnostic commandPower save mode Power SaveActive mode Active idle modeSleep mode Standby modeSpare area Power commandsDefect Processing Track slip processing Alternating processing for defective sectorsSector slip processing Automatic alternating processing Automatic alternating processing8MB buffer 8,388,608 bytes Read-ahead CacheData buffer structure Caching operation Commands that are targets of cachingData that is a target of caching Invalidating caching-target dataSmart Miss-hit Using the read segment bufferSequential hit Full hit Partial hit Write Cache Command that are targets of cachingCache operation Invalidation of cached dataReset response Status report in the event of an errorCaching function when power supply is turned on Enabling and disablingWrite Cache This page is intentionally left blank Glossary Rotational delay Power save modePIO Programmed input-output PositioningVCM StatusThis page is intentionally left blank Acronyms and Abbreviations This page is intentionally left blank AAM IndexIndex Host pausing ultra DMA data Read Native MAX Address Read Sectors CommandSurface temperature measurement This page is intentionally left blank Japan Comment FormThis page is intentionally left blank C141-E221-02EN This page is intentionally left blank
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Fujitsu's MHV series of hard disk drives, specifically the MHV2040AS, MHV2080AS, and MHV2060AS models, are designed to deliver efficient performance and reliability for a range of applications, particularly in desktop computing and entry-level servers. Each of these drives adheres to the Serial ATA (SATA) interface, which ensures compatibility across a wide range of systems and is known for its cost-effectiveness and simplicity.

The MHV2040AS features a storage capacity of 40GB, making it suitable for basic computing tasks including document editing, web browsing, and media playback. The MHV2060AS steps it up with a 60GB capacity, allowing for increased data storage needs while still maintaining a high level of performance. The largest of the trio, the MHV2080AS, offers an impressive 80GB of space, positioning it well for users who require additional room for applications, games, and multimedia files.

All drives in this series are equipped with a rotational speed of 5400 RPM, which strikes a balance between speed and power consumption. This speed is adequate for everyday tasks and allows for quick boot times and file access, making them ideal for home and small office environments. Additionally, the drives feature an average latency of 5.5 milliseconds, contributing to their overall performance in retrieving data.

In terms of technology, the MHV series employs a fluid dynamic bearing (FDB) motor, which not only enhances reliability but also reduces noise levels during operation. The FDB technology helps improve the longevity of the drives by minimizing wear on mechanical components. This characteristic is particularly important for users seeking quieter drives, especially in work environments that require minimal disruption.

The drives also incorporate advanced power management features that significantly reduce power consumption, making them an environmentally friendly choice for users mindful of their carbon footprint. These drives are equipped with energy-saving modes that optimize their performance when not in full use, ensuring lower operational costs and longer lifespan.

Overall, the Fujitsu MHV2040AS, MHV2080AS, and MHV2060AS hard drives provide a solid solution for users looking for dependable storage with a range of capacities to fit their needs. Their performance, combined with noise reduction technologies and energy efficiency, makes them a notable choice for various computing environments, from single-user desktops to small business applications.
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