Fujitsu MHV2060AS, MHV2080AS, MHV2040AS manual Ultra DMA CRC rules

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5.5 Ultra DMA Feature Set

13)The host shall neither negate STOP nor HSTROBE until at least tACK after negating DMACK-.

14)The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK after negating DMACK.

5.5.5Ultra DMA CRC rules

The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra DMA burst, and reporting any error that occurs at the end of a command.

a)Both the host and the device shall have a 16-bit CRC calculation function.

b)Both the host and the device shall calculate a CRC value for each Ultra DMA burst.

c)The CRC function in the host and the device shall be initialized with a seed of 4ABAh at the beginning of an Ultra DMA burst before any data is transferred.

d)For each STROBE transition used for data transfer, both the host and the device shall calculate a new CRC value by applying the CRC polynomial to the current value of their individual CRC functions and the word being transferred. CRC is not calculated for the return of STROBE to the asserted state after the Ultra DMA burst termination request has been acknowledged.

e)At the end of any Ultra DMA burst the host shall send the results of its CRC calculation function to the device on DD (15:0) with the negation of DMACK-.

f)The device shall then compare the CRC data from the host with the calculated value in its own CRC calculation function. If the two values do not match, the device shall save the error and report it at the end of the command. A subsequent Ultra DMA burst for the same command that does not have a CRC error shall not clear an error saved from a previous Ultra DMa burst in the same command. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred.

g)For READ DMA or WRITE DMA commands: When a CRC error is detected, it shall be reported by setting both ICRC and ABRT (bit 7 and bit 2 in the Error register) to one. ICRC is defined as the "Interface CRC Error" bit. The host shall respond to this error by re-issuing the command.

h)A host may send extra data words on the last Ultra DMA burst of a data out command. If a device determines that all data has been transferred for a command, the device shall terminate the burst. A device may have already received more data words than were required for the command. These extra words are used by both the host and the device to calculate the CRC, but, on an Ultra DMA data out burst, the extra words shall be discarded by the device.

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Contents Disk Drive Product Manual MHV2080AS, MHV2060AS, MHV2040ASHandling of This Manual For Safe OperationRevision History This page is intentionally left blank Overview of Manual PrefaceOperating Environment Conventions for Alert MessagesConventions Liability Exception This page is intentionally left blank Important Alert Messages Important Alert ItemsDamage Interface cable connection This page is intentionally left blank Disk Drive Product Manual Disk Drive Maintenance ManualManual Organization MHV2080ASThis page is intentionally left blank Contents Theory of Device Operation Installation ConditionsInterface Contents101 Write Multiple EXT X’39’ Option customizing Operations Glossary GL-1 Acronyms and Abbreviations AB-1 Index IN-1 Figures IllustrationsExecution example of Read Multiple command Examples of model names and product numbers Tables127 This page is intentionally left blank Device Overview Functions and performance FeaturesAdaptability Data buffer Error correction and retry by ECCHigh resistance against shock Connection to ATA interfaceMHV2080AS MHV2060AS MHV2040AS Device SpecificationsSpecifications summary Specifications 1Examples of model names and product numbers Model and product numberInput Voltage Power RequirementsRipple Current and power dissipation Current Requirements and Power DissipationEnvironmental specifications Environmental SpecificationsCurrent fluctuation Typ. at +5 V when power is turned on Power on/off sequenceShock and Vibration Acoustic noise specificationShock and vibration specification Acoustic NoiseMean time between failures Mtbf Service lifeData assurance in the event of power failure ReliabilityMedia Defects Error RateUnrecoverable read error Positioning errorAdvanced Power Management Advanced Power Management This page is intentionally left blank Device Configuration Device Configuration Read/write circuit System ConfigurationATA interface 2 1 drive connection3 2 drives connection 2 drives configurationInstallation Conditions Dimensions DimensionsIntegration Guidance C141-E144 MountingOrientation Limitation of mounting FramePCA Location of breather Ambient temperature Handling cautions Service areaHandling cautions Cable Connections Device connectorFCI Cable connector specificationsCable connector specifications Device connectionPower supply connector CN1 Jumper SettingsLocation of setting jumpers Master drive-slave drive setting Factory default setting14 Csel setting Csel setting16 Example 2 of cable select Power up in standby settingTheory of Device Operation Spindle OutlineSubassemblies DiskSpindle motor driver circuit Circuit ConfigurationAir filter Servo circuitPower supply configuration PCA Power-on operation sequence Power-on SequenceSelf-calibration Self-calibration contentsExecution timing of self-calibration Command processing during self-calibrationWrite precompensation Read/write CircuitRead/write preamplifier PreAMP Write circuitAGC circuit Read circuitProgrammable filter circuit Viterbi detection circuit Digital PLL circuitFIR circuit D converter circuitServo control circuit Servo ControlA converter DAC Power amplifierMicroprocessor unit MPU Servo burst capture circuitVCM current sense resistor CSR Driver circuitOuter guard band Data-surface servo formatInner guard band Data areaPhysical sector servo configuration on disk surface Servo frame format Track following operation Actuator motor controlOperation to move the head to the reference cylinder Seek operationSpindle motor control Start modeAcceleration mode Stable rotation modeThis page is intentionally left blank Interface Physical Interface Interface signalsDasp GND Signal assignment on the connectorSignal assignment on the interface connector DA1 PDIAG-, Cblid DA0 DA2Dior MstrDiow StopIordy PdiagCblid DaspLogical Interface I/O registers 1 I/O registersDA2 DA1 DA0 UNC Idnf Command block registersError register X’1F1’ Data register X’1F0’Sector Count register X’1F2’ Features register X’1F1’Cylinder Low register X’1F4’ Sector Number register X’1F3’Cylinder High register X’1F5’ BSY Device/Head register X’1F6’DEV HS3 HS2 HS1 HS0 Status register X’1F7’Interface Control block registers Command register X’1F7’Alternate Status register X’3F6’ HOB Srst Host CommandsCommand code and parameters Device Control register X’3F6’Command Name Command code and parameters 1Parameter Used EXT Write Multiple FUA EXT Flush Cache EXT Command code and parameters 2Host Commands Command descriptions Host Commands Recalibrate X’10’ to X’1F’ MSB Read Sectors X’20’ or X’21’End head No. / LBA MSB Write Sectors X’30’ or X’31’ 1F7HST Status information 1F6HDH Write Verify X’3C’ Read Verify Sectors X’40’ or X’41’ Seek X’70’ to X’7F’ Diagnostic code Execute Device Diagnostic X’90’Device responds to this command with the result of power-on Initialize Device Parameters X’91’ Download Microcode X’92’ Operation of Download Microcode Standby Immediate X’94’ or X’E0’ Unload Feature Unload Immediate Command Host Commands Standby X’96’ or X’E2’ Idle X’97’ or X’E3’ Interface ’FF’ Check Power Mode X’98’ or X’E5’Sleep X’99’ or X’E6’ Smart X’B0 Features register values subcommands and functions 1 Smart Read LOG Features register values subcommands and functions 2Smart Enable Operations Smart Disable Operations’DB’ Smart ENABLE/DISABLE Auto OFF-LINE Features register values subcommands and functions 3Smart Return Status Host Commands 1FF Format of device attribute value dataFormat of insurance failure threshold value data Attribute ID Data format version numberRaw attribute value Status FlagCurrent attribute value Attribute value for the worst case so farSelf-test execution status 10 Off-line data collection status11 Self-test execution status 13 Failure prediction capability flag Off-line data collection capability12 Off-line data collection capability Failure prediction capability flagInsurance failure threshold Error logging capability14 Error logging capability Check sumSmart error logging 16 Data format of Smart Summary Error Log 17 Data format of Smart Comprehensive Error Log Command data structureError data structure Total number of drive errorsSelf-test number Smart self-test18 Smart self-test log data format 1FCCurrent span under test 19 Selective self-test log data structureTest span Current LBA under test20 Selective self-test feature flags Feature FlagsSelective Self-test pending time min Device Configuration Identify Device Configuration XB1Device Configuration Restore Device Configuration FreezeDevice Configuration SET FR = C3h Device Configuration Restore FR = C0hDevice Configuration Freeze Lock FR = C1h Device Configuration Identify FR = C2hInterface 21 Device Configuration Identify data structure 1/2 21 Device Configuration Identify data structure 2/2 Read Multiple X’C4’ Execution example of Read Multiple commandMSB Write Multiple X’C5’ Interface SET Multiple Mode X’C6’ Interface Read DMA X’C8’ or X’C9’ End head No. / LBA MSB Write DMA X’CA’ or X’CB’ Interface Read Buffer X’E4’ Flush Cache X’E7’ Write Buffer X’E8’ Identify Device X’EC’ Identify Device DMA X’EE’ ’3FFF’ 22 Information to be read by Identify Device command 122 Information to be read by Identify Device command 2 3FFF Command without interrupt supports 2, 4, 8 and 16 sectors = Supports the Host Protected Area feature set = Supports the CFA Compact Flash Association feature set Interface Write Stream EXT Interface Host Commands Word Bit Reserved Security level High, 1 Maximum ’CC’ SET Features X’EF’23 Features register values and settable modes ’BB’Data Transfer Mode Advanced Power Management APM Automatic Acoustic Management AAM 24 Contents of Security SET Password data Interface When the user password is selected When the master password is selectedSecurity UNLOCKX’F2’ Interface Security Erase Prepare X’F3’ Security Erase Unit X’F4’ Security Freeze Lock X’F5’ Interface 26 Contents of security password Interface Read Native MAX Address X’F8’ SET MAX Address SET MAX X’F9’SET MAX SET Password FR = 01h SET MAX Lock FR = 02h SET MAX Unlock FR = 03h SET MAX Freeze Lock FR = 04h Host Commands Read Sectors EXT X’24’ Option customizing Description Read DMA EXT X’25’ Option customizing Description Error reporting conditions Read Multiple EXT X’29’ Option customizing Description Read LOG EXT X2F Optional command Customize Description Host Commands Write Sectors EXT X’34’ Option customizing Description Write DMA EXT X’35’ Option customizing Description SET MAX Address EXT X’37’ Option customizing Description SET MAX LBA Write Multiple EXT X’39’ Option customizing Description Write DMA FUA EXT X’3D’ Option customizing Description Write LOG EXT X’3F’ Optional command Customize Description Host Commands Read Verify Sectors EXT X’42 Option customizing Description Write Multiple FUA EXT X’CE’ Option customizing Description Flush Cache EXT X’EA’ Option customizing Description 27 Command code and parameters 1 Error posting27 Command code and parameters 2 PIO Data transferring commands from device to host Command ProtocolExecute Device Diagnostic Initialize Device Parameters Read Sectors Command protocol Protocol for command abort PIO Data transferring commands from host to device Write Sectors command protocol Commands without data transfer Read DMA EXT Write DMA EXT/FUA EXT Indentify Device DMA Other commandsDMA data transfer commands Read Multiple EXT Write Multiple EXT/FUA EXT SleepNormal DMA data transfer Overview Ultra DMA Feature SetUltra DMA data in commands Phases of operationInitiating an Ultra DMA data in burst Data in transfer Pausing an Ultra DMA data in burstTerminating an Ultra DMA data in burst Ultra DMA Feature Set Interface Initiating an Ultra DMA data out burst Ultra DMA data out commandsData out transfer Pausing an Ultra DMA data out burstTerminating an Ultra DMA data out burst Interface Ultra DMA CRC rules DIOW-STOP Series termination required for Ultra DMA28 Recommended series termination for Ultra DMA DIOR-HDMARDY-HSTROBEPIO data transfer TimingPIO data transfer timing Multiword data transfer 10 Multiword DMA data transfer timing mode11 Initiating an Ultra DMA data in burst Ultra DMA data transferStrobe Name Mode CommentMIN MAX 29 Ultra DMA data burst timing requirements 230 Ultra DMA sender and recipient timing requirements Mode Name CommentDD150 at host Sustained Ultra DMA data in burstDstrobe at device DD150 at device Dstrobe at hostHdmardy Host pausing an Ultra DMA data in burstDmarq DmackStop Device terminating an Ultra DMA data in burstHost Host terminating an Ultra DMA data in burstDA0, DA1, DA2 CS0, CS1 16 Initiating an Ultra DMA data out burst Hstrobe at host DD150 at host Sustained Ultra DMA data out burstHstrobe at device DD150 at device Device DMACK- host Stop host DDMARDY- device Device pausing an Ultra DMA data out burstHstrobe host DD150 Host 19 Host terminating an Ultra DMA data out burst Host terminating an Ultra DMA data out burstDmarq device DMACK- host Device terminating an Ultra DMA data out burstDD150 Host Master and slave devices are present 2-drives configuration Power-on and resetOnly master device is present Operations Response to power-on Device Response to the ResetResponse to power-on Response to hardware resetResponse to hardware reset Response to software reset Response to software resetResponse to diagnostic command Response to diagnostic commandActive idle mode Power SavePower save mode Active modeSleep mode Standby modeDefect Processing Power commandsSpare area Sector slip processing Alternating processing for defective sectorsTrack slip processing Automatic alternating processing Automatic alternating processingData buffer structure Read-ahead Cache8MB buffer 8,388,608 bytes Invalidating caching-target data Commands that are targets of cachingCaching operation Data that is a target of cachingSmart Miss-hit Using the read segment bufferSequential hit Full hit Partial hit Invalidation of cached data Command that are targets of cachingWrite Cache Cache operationEnabling and disabling Status report in the event of an errorReset response Caching function when power supply is turned onWrite Cache This page is intentionally left blank Glossary Positioning Power save modeRotational delay PIO Programmed input-outputVCM StatusThis page is intentionally left blank Acronyms and Abbreviations This page is intentionally left blank AAM IndexIndex Host pausing ultra DMA data Read Native MAX Address Read Sectors CommandSurface temperature measurement This page is intentionally left blank Japan Comment FormThis page is intentionally left blank C141-E221-02EN This page is intentionally left blank
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MHV2060AS, MHV2080AS, MHV2040AS specifications

Fujitsu's MHV series of hard disk drives, specifically the MHV2040AS, MHV2080AS, and MHV2060AS models, are designed to deliver efficient performance and reliability for a range of applications, particularly in desktop computing and entry-level servers. Each of these drives adheres to the Serial ATA (SATA) interface, which ensures compatibility across a wide range of systems and is known for its cost-effectiveness and simplicity.

The MHV2040AS features a storage capacity of 40GB, making it suitable for basic computing tasks including document editing, web browsing, and media playback. The MHV2060AS steps it up with a 60GB capacity, allowing for increased data storage needs while still maintaining a high level of performance. The largest of the trio, the MHV2080AS, offers an impressive 80GB of space, positioning it well for users who require additional room for applications, games, and multimedia files.

All drives in this series are equipped with a rotational speed of 5400 RPM, which strikes a balance between speed and power consumption. This speed is adequate for everyday tasks and allows for quick boot times and file access, making them ideal for home and small office environments. Additionally, the drives feature an average latency of 5.5 milliseconds, contributing to their overall performance in retrieving data.

In terms of technology, the MHV series employs a fluid dynamic bearing (FDB) motor, which not only enhances reliability but also reduces noise levels during operation. The FDB technology helps improve the longevity of the drives by minimizing wear on mechanical components. This characteristic is particularly important for users seeking quieter drives, especially in work environments that require minimal disruption.

The drives also incorporate advanced power management features that significantly reduce power consumption, making them an environmentally friendly choice for users mindful of their carbon footprint. These drives are equipped with energy-saving modes that optimize their performance when not in full use, ensuring lower operational costs and longer lifespan.

Overall, the Fujitsu MHV2040AS, MHV2080AS, and MHV2060AS hard drives provide a solid solution for users looking for dependable storage with a range of capacities to fit their needs. Their performance, combined with noise reduction technologies and energy efficiency, makes them a notable choice for various computing environments, from single-user desktops to small business applications.
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