Fujitsu MHV2080AS, MHV2060AS, MHV2040AS manual Pdiag, Cblid, Dasp, Iordy, Ddmardy

Page 81

 

 

5.1 Physical Interface

[Signal]

[I/O]

[Description]

CS0-

I

Chip select signal decoded from the host address bus. This signal

 

 

is used by the host to select the command block registers.

CS1-

I

Chip select signal decoded from the host address bus. This signal

 

 

is used by the host to select the control block registers.

DA 0-2

I

Binary decoded address signals asserted by the host to access task

 

 

file registers.

KEY

-

Key pin for prevention of erroneous connector insertion

PDIAG-

I/O

This signal is an input mode for the master device and an output

 

 

mode for the slave device in a daisy chain configuration. This

 

 

signal indicates that the slave device has been completed self-

 

 

diagnostics.

 

 

This signal is pulled up to +5 V through 10 kΩ resistor at each device.

CBLID-

I/O

This signal is used to detect the type of cable installed in the

 

 

system.

 

 

This signal is pulled up to +5 V through 10 kΩ resistor at each device.

DASP-

I/O

This is a time-multiplexed signal that indicates that the device is

 

 

active and a slave device is present.

 

 

This signal is pulled up to +5 V through 10 kΩ resistor at each device.

IORDY

O

This signal requests the host system to delay the transfer cycle

 

 

when the device is not ready to respond to a data transfer request

 

 

from the host system.

DDMARDY-

O

Flow control signal for Ultra DMA data Out transfer (WRITE

 

 

DMA command). This signal is asserted by the device to inform

 

 

the host that the device is ready to receive the Ultra DMA data

 

 

Out transfer. The device can negate the DDMARDY- signal to

 

 

suspend the Ultra DMA data Out transfer.

DSTROBE

O

Data In Strobe signal from the device during Ultra DMA data In

 

 

transfer. Both the rising and falling edges of the DSTROBE

 

 

signal latch data from Data 15-0 into the host. The device can

 

 

suspend the inversion of the DSTROBE signal to suspend the

 

 

Ultra DMA data In transfer.

CSEL

I

This signal to configure the device as a master or a slave device.

 

 

− When CSEL signal is grounded, the IDD is a master device.

 

 

− When CSEL signal is open, the IDD is a slave device.

 

 

This signal is pulled up with 240 kΩ resistor at each device.

DMACK-

I

The host system asserts this signal as a response that the host

 

 

system receives data or to indicate that data is valid.

C141-E221

5-5

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Contents Disk Drive Product Manual MHV2080AS, MHV2060AS, MHV2040ASHandling of This Manual For Safe OperationRevision History This page is intentionally left blank Overview of Manual PrefaceConventions for Alert Messages Operating EnvironmentConventions Liability Exception This page is intentionally left blank Important Alert Items Important Alert MessagesDamage Interface cable connection This page is intentionally left blank Manual Organization Disk Drive Maintenance ManualMHV2080AS Disk Drive Product ManualThis page is intentionally left blank Contents Theory of Device Operation Installation ConditionsInterface Contents101 Write Multiple EXT X’39’ Option customizing Operations Glossary GL-1 Acronyms and Abbreviations AB-1 Index IN-1 Figures IllustrationsExecution example of Read Multiple command Examples of model names and product numbers Tables127 This page is intentionally left blank Device Overview Features Functions and performanceAdaptability High resistance against shock Error correction and retry by ECCConnection to ATA interface Data bufferSpecifications summary Device SpecificationsSpecifications 1 MHV2080AS MHV2060AS MHV2040ASExamples of model names and product numbers Model and product numberPower Requirements Input VoltageRipple Current and power dissipation Current Requirements and Power DissipationCurrent fluctuation Typ. at +5 V when power is turned on Environmental SpecificationsPower on/off sequence Environmental specificationsShock and vibration specification Acoustic noise specificationAcoustic Noise Shock and VibrationData assurance in the event of power failure Service lifeReliability Mean time between failures MtbfUnrecoverable read error Error RatePositioning error Media DefectsAdvanced Power Management Advanced Power Management This page is intentionally left blank Device Configuration Device Configuration ATA interface System Configuration2 1 drive connection Read/write circuit3 2 drives connection 2 drives configurationInstallation Conditions Dimensions DimensionsMounting Integration Guidance C141-E144Orientation Frame Limitation of mountingPCA Location of breather Ambient temperature Handling cautions Service areaHandling cautions Cable Connections Device connectorCable connector specifications Cable connector specificationsDevice connection FCIJumper Settings Power supply connector CN1Location of setting jumpers Master drive-slave drive setting Factory default setting14 Csel setting Csel setting16 Example 2 of cable select Power up in standby settingTheory of Device Operation Subassemblies OutlineDisk SpindleAir filter Circuit ConfigurationServo circuit Spindle motor driver circuitPower supply configuration PCA Power-on operation sequence Power-on SequenceSelf-calibration Self-calibration contentsExecution timing of self-calibration Command processing during self-calibrationRead/write preamplifier PreAMP Read/write CircuitWrite circuit Write precompensationRead circuit AGC circuitProgrammable filter circuit FIR circuit Digital PLL circuitD converter circuit Viterbi detection circuitServo control circuit Servo ControlMicroprocessor unit MPU Power amplifierServo burst capture circuit A converter DACVCM current sense resistor CSR Driver circuitInner guard band Data-surface servo formatData area Outer guard bandPhysical sector servo configuration on disk surface Servo frame format Operation to move the head to the reference cylinder Actuator motor controlSeek operation Track following operationAcceleration mode Start modeStable rotation mode Spindle motor controlThis page is intentionally left blank Interface Physical Interface Interface signalsSignal assignment on the interface connector Signal assignment on the connectorDA1 PDIAG-, Cblid DA0 DA2 Dasp GNDDiow MstrStop DiorCblid PdiagDasp IordyLogical Interface 1 I/O registers I/O registersDA2 DA1 DA0 Error register X’1F1’ Command block registersData register X’1F0’ UNC IdnfSector Count register X’1F2’ Features register X’1F1’Sector Number register X’1F3’ Cylinder Low register X’1F4’Cylinder High register X’1F5’ DEV HS3 HS2 HS1 HS0 Device/Head register X’1F6’Status register X’1F7’ BSYInterface Command register X’1F7’ Control block registersAlternate Status register X’3F6’ Command code and parameters Host CommandsDevice Control register X’3F6’ HOB SrstCommand code and parameters 1 Command NameParameter Used EXT Write Multiple FUA EXT Flush Cache EXT Command code and parameters 2Host Commands Command descriptions Host Commands Recalibrate X’10’ to X’1F’ MSB Read Sectors X’20’ or X’21’End head No. / LBA MSB Write Sectors X’30’ or X’31’ 1F7HST Status information 1F6HDH Write Verify X’3C’ Read Verify Sectors X’40’ or X’41’ Seek X’70’ to X’7F’ Diagnostic code Execute Device Diagnostic X’90’Device responds to this command with the result of power-on Initialize Device Parameters X’91’ Download Microcode X’92’ Operation of Download Microcode Standby Immediate X’94’ or X’E0’ Unload Feature Unload Immediate Command Host Commands Standby X’96’ or X’E2’ Idle X’97’ or X’E3’ Interface ’FF’ Check Power Mode X’98’ or X’E5’Sleep X’99’ or X’E6’ Smart X’B0 Features register values subcommands and functions 1 Smart Enable Operations Features register values subcommands and functions 2Smart Disable Operations Smart Read LOGFeatures register values subcommands and functions 3 ’DB’ Smart ENABLE/DISABLE Auto OFF-LINESmart Return Status Host Commands Format of device attribute value data 1FFFormat of insurance failure threshold value data Attribute ID Data format version numberCurrent attribute value Status FlagAttribute value for the worst case so far Raw attribute value10 Off-line data collection status Self-test execution status11 Self-test execution status 12 Off-line data collection capability Off-line data collection capabilityFailure prediction capability flag 13 Failure prediction capability flag14 Error logging capability Error logging capabilityCheck sum Insurance failure thresholdSmart error logging 16 Data format of Smart Summary Error Log Error data structure Command data structureTotal number of drive errors 17 Data format of Smart Comprehensive Error Log18 Smart self-test log data format Smart self-test1FC Self-test numberTest span 19 Selective self-test log data structureCurrent LBA under test Current span under testFeature Flags 20 Selective self-test feature flagsSelective Self-test pending time min Device Configuration Restore Device Configuration XB1Device Configuration Freeze Device Configuration IdentifyDevice Configuration Freeze Lock FR = C1h Device Configuration Restore FR = C0hDevice Configuration Identify FR = C2h Device Configuration SET FR = C3hInterface 21 Device Configuration Identify data structure 1/2 21 Device Configuration Identify data structure 2/2 Read Multiple X’C4’ Execution example of Read Multiple commandMSB Write Multiple X’C5’ Interface SET Multiple Mode X’C6’ Interface Read DMA X’C8’ or X’C9’ End head No. / LBA MSB Write DMA X’CA’ or X’CB’ Interface Read Buffer X’E4’ Flush Cache X’E7’ Write Buffer X’E8’ Identify Device X’EC’ Identify Device DMA X’EE’ ’3FFF’ 22 Information to be read by Identify Device command 122 Information to be read by Identify Device command 2 3FFF Command without interrupt supports 2, 4, 8 and 16 sectors = Supports the Host Protected Area feature set = Supports the CFA Compact Flash Association feature set Interface Write Stream EXT Interface Host Commands Word Bit Reserved Security level High, 1 Maximum 23 Features register values and settable modes SET Features X’EF’’BB’ ’CC’Data Transfer Mode Advanced Power Management APM Automatic Acoustic Management AAM 24 Contents of Security SET Password data Interface When the master password is selected When the user password is selectedSecurity UNLOCKX’F2’ Interface Security Erase Prepare X’F3’ Security Erase Unit X’F4’ Security Freeze Lock X’F5’ Interface 26 Contents of security password Interface Read Native MAX Address X’F8’ SET MAX Address SET MAX X’F9’SET MAX SET Password FR = 01h SET MAX Lock FR = 02h SET MAX Unlock FR = 03h SET MAX Freeze Lock FR = 04h Host Commands Read Sectors EXT X’24’ Option customizing Description Read DMA EXT X’25’ Option customizing Description Error reporting conditions Read Multiple EXT X’29’ Option customizing Description Read LOG EXT X2F Optional command Customize Description Host Commands Write Sectors EXT X’34’ Option customizing Description Write DMA EXT X’35’ Option customizing Description SET MAX Address EXT X’37’ Option customizing Description SET MAX LBA Write Multiple EXT X’39’ Option customizing Description Write DMA FUA EXT X’3D’ Option customizing Description Write LOG EXT X’3F’ Optional command Customize Description Host Commands Read Verify Sectors EXT X’42 Option customizing Description Write Multiple FUA EXT X’CE’ Option customizing Description Flush Cache EXT X’EA’ Option customizing Description 27 Command code and parameters 1 Error posting27 Command code and parameters 2 Command Protocol PIO Data transferring commands from device to hostExecute Device Diagnostic Initialize Device Parameters Read Sectors Command protocol Protocol for command abort PIO Data transferring commands from host to device Write Sectors command protocol Commands without data transfer DMA data transfer commands Other commandsRead Multiple EXT Write Multiple EXT/FUA EXT Sleep Read DMA EXT Write DMA EXT/FUA EXT Indentify Device DMANormal DMA data transfer Overview Ultra DMA Feature SetPhases of operation Ultra DMA data in commandsInitiating an Ultra DMA data in burst Data in transfer Pausing an Ultra DMA data in burstTerminating an Ultra DMA data in burst Ultra DMA Feature Set Interface Initiating an Ultra DMA data out burst Ultra DMA data out commandsData out transfer Pausing an Ultra DMA data out burstTerminating an Ultra DMA data out burst Interface Ultra DMA CRC rules 28 Recommended series termination for Ultra DMA Series termination required for Ultra DMADIOR-HDMARDY-HSTROBE DIOW-STOPTiming PIO data transferPIO data transfer timing Multiword data transfer 10 Multiword DMA data transfer timing mode11 Initiating an Ultra DMA data in burst Ultra DMA data transferStrobe Name Mode CommentMIN MAX 29 Ultra DMA data burst timing requirements 230 Ultra DMA sender and recipient timing requirements Mode Name CommentDstrobe at device Sustained Ultra DMA data in burstDD150 at device Dstrobe at host DD150 at hostDmarq Host pausing an Ultra DMA data in burstDmack HdmardyStop Device terminating an Ultra DMA data in burstHost terminating an Ultra DMA data in burst HostDA0, DA1, DA2 CS0, CS1 16 Initiating an Ultra DMA data out burst Sustained Ultra DMA data out burst Hstrobe at host DD150 at hostHstrobe at device DD150 at device Device pausing an Ultra DMA data out burst Device DMACK- host Stop host DDMARDY- deviceHstrobe host DD150 Host 19 Host terminating an Ultra DMA data out burst Host terminating an Ultra DMA data out burstDevice terminating an Ultra DMA data out burst Dmarq device DMACK- hostDD150 Host Power-on and reset Master and slave devices are present 2-drives configurationOnly master device is present Operations Response to power-on Device Response to the ResetResponse to power-on Response to hardware resetResponse to hardware reset Response to software reset Response to software resetResponse to diagnostic command Response to diagnostic commandPower save mode Power SaveActive mode Active idle modeSleep mode Standby modePower commands Defect ProcessingSpare area Alternating processing for defective sectors Sector slip processingTrack slip processing Automatic alternating processing Automatic alternating processingRead-ahead Cache Data buffer structure8MB buffer 8,388,608 bytes Caching operation Commands that are targets of cachingData that is a target of caching Invalidating caching-target dataSmart Miss-hit Using the read segment bufferSequential hit Full hit Partial hit Write Cache Command that are targets of cachingCache operation Invalidation of cached dataReset response Status report in the event of an errorCaching function when power supply is turned on Enabling and disablingWrite Cache This page is intentionally left blank Glossary Rotational delay Power save modePIO Programmed input-output PositioningVCM StatusThis page is intentionally left blank Acronyms and Abbreviations This page is intentionally left blank AAM IndexIndex Host pausing ultra DMA data Read Native MAX Address Read Sectors CommandSurface temperature measurement This page is intentionally left blank Japan Comment FormThis page is intentionally left blank C141-E221-02EN This page is intentionally left blank
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MHV2060AS, MHV2080AS, MHV2040AS specifications

Fujitsu's MHV series of hard disk drives, specifically the MHV2040AS, MHV2080AS, and MHV2060AS models, are designed to deliver efficient performance and reliability for a range of applications, particularly in desktop computing and entry-level servers. Each of these drives adheres to the Serial ATA (SATA) interface, which ensures compatibility across a wide range of systems and is known for its cost-effectiveness and simplicity.

The MHV2040AS features a storage capacity of 40GB, making it suitable for basic computing tasks including document editing, web browsing, and media playback. The MHV2060AS steps it up with a 60GB capacity, allowing for increased data storage needs while still maintaining a high level of performance. The largest of the trio, the MHV2080AS, offers an impressive 80GB of space, positioning it well for users who require additional room for applications, games, and multimedia files.

All drives in this series are equipped with a rotational speed of 5400 RPM, which strikes a balance between speed and power consumption. This speed is adequate for everyday tasks and allows for quick boot times and file access, making them ideal for home and small office environments. Additionally, the drives feature an average latency of 5.5 milliseconds, contributing to their overall performance in retrieving data.

In terms of technology, the MHV series employs a fluid dynamic bearing (FDB) motor, which not only enhances reliability but also reduces noise levels during operation. The FDB technology helps improve the longevity of the drives by minimizing wear on mechanical components. This characteristic is particularly important for users seeking quieter drives, especially in work environments that require minimal disruption.

The drives also incorporate advanced power management features that significantly reduce power consumption, making them an environmentally friendly choice for users mindful of their carbon footprint. These drives are equipped with energy-saving modes that optimize their performance when not in full use, ensuring lower operational costs and longer lifespan.

Overall, the Fujitsu MHV2040AS, MHV2080AS, and MHV2060AS hard drives provide a solid solution for users looking for dependable storage with a range of capacities to fit their needs. Their performance, combined with noise reduction technologies and energy efficiency, makes them a notable choice for various computing environments, from single-user desktops to small business applications.
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